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74ALVC32PW

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Nexperia Logic ICs, TSSOP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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74ALVC32PW

Nexperia · Logic ICs · TSSOP-14

74ALVC32PW from Nexperia, in a TSSOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 1A input Data input 1A of gate 1; inputs are overvoltage tolerant to 3.6 V and use Schmitt trigger action to tolerate slow rise and fall times.
2 1B input Data input 1B of gate 1; inputs are overvoltage tolerant to 3.6 V and use Schmitt trigger action to tolerate slow rise and fall times.
3 1Y output Data output 1Y of gate 1; IOFF circuitry disables this output during power-down to prevent backflow current, and output current is limited to ±50 mA.
4 2A input Data input 2A of gate 2; inputs are overvoltage tolerant to 3.6 V and use Schmitt trigger action to tolerate slow rise and fall times.
5 2B input Data input 2B of gate 2; inputs are overvoltage tolerant to 3.6 V and use Schmitt trigger action to tolerate slow rise and fall times.
6 2Y output Data output 2Y of gate 2; IOFF circuitry disables this output during power-down to prevent backflow current, and output current is limited to ±50 mA.
7 GND power_in Ground (0 V) reference for all voltages in the device.
8 3Y output Data output 3Y of gate 3; IOFF circuitry disables this output during power-down to prevent backflow current, and output current is limited to ±50 mA.
9 3A input Data input 3A of gate 3; inputs are overvoltage tolerant to 3.6 V and use Schmitt trigger action to tolerate slow rise and fall times.
10 3B input Data input 3B of gate 3; inputs are overvoltage tolerant to 3.6 V and use Schmitt trigger action to tolerate slow rise and fall times.
11 4Y output Data output 4Y of gate 4; IOFF circuitry disables this output during power-down to prevent backflow current, and output current is limited to ±50 mA.
12 4A input Data input 4A of gate 4; inputs are overvoltage tolerant to 3.6 V and use Schmitt trigger action to tolerate slow rise and fall times.
13 4B input Data input 4B of gate 4; inputs are overvoltage tolerant to 3.6 V and use Schmitt trigger action to tolerate slow rise and fall times.
14 VCC power_in Supply voltage with a recommended operating range of 1.65 V to 3.6 V.

Key specifications

Parameter Value
Manufacturer Nexperia
Package TSSOP-14
Category Logic ICs
Pins 14

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
supply voltage VCC -0.5 4.6 V 3
input voltage VI -0.5 4.6 V 3
output voltage power-down mode VO -0.5 4.6 V power-down mode; VCC = 0 V 3
input clamping current IIK -50 mA VI < 0 V 3
output clamping current IOK -50 50 mA VO > VCC or VO < 0 V 3
output current IO -50 50 mA VO = 0 V to VCC 3
supply current ICC 100 mA 3
ground current IGND -100 mA 3
storage temperature Tstg -65 150 °C 3
total power dissipation Ptot 500 mW Tamb = -40 °C to +125 °C 3
supply voltage VCC 1.65 3.6 V 3
input voltage VI 0 3.6 V 3
output voltage power-down mode VO 0 3.6 V power-down mode; VCC = 0 V 3
ambient temperature Tamb -40 125 °C in free air 3
input transition rise and fall rate Δt/ΔV 0 20 ns/V VCC = 1.65 V to 2.7 V 3
input transition rise and fall rate Δt/ΔV 0 10 ns/V VCC = 2.7 V to 3.6 V 3
HIGH-level input voltage VIH 1.7 V VCC = 2.3 V to 2.7 V 4
HIGH-level input voltage VIH 2 V VCC = 2.7 V to 3.6 V 4
LOW-level input voltage VIL 0.7 V VCC = 2.3 V to 2.7 V 4
LOW-level input voltage VIL 0.8 V VCC = 2.7 V to 3.6 V 4
HIGH-level output voltage VOH 1.25 1.51 V VI = VIH or VIL; IO = -6 mA; VCC = 1.65 V 4
HIGH-level output voltage VOH 1.8 2.1 V VI = VIH or VIL; IO = -12 mA; VCC = 2.3 V 4
HIGH-level output voltage VOH 1.7 2.01 V VI = VIH or VIL; IO = -18 mA; VCC = 2.3 V 4
HIGH-level output voltage VOH 2.2 2.53 V VI = VIH or VIL; IO = -12 mA; VCC = 2.7 V 4
HIGH-level output voltage VOH 2.4 2.76 V VI = VIH or VIL; IO = -18 mA; VCC = 3.0 V 4
HIGH-level output voltage VOH 2.2 2.68 V VI = VIH or VIL; IO = -24 mA; VCC = 3.0 V 4
LOW-level output voltage VOL 0.2 V VI = VIH or VIL; IO = 100 μA; VCC = 1.65 V to 3.6 V 4
LOW-level output voltage VOL 0.11 0.3 V VI = VIH or VIL; IO = 6 mA; VCC = 1.65 V 4
LOW-level output voltage VOL 0.17 0.4 V VI = VIH or VIL; IO = 12 mA; VCC = 2.3 V 4
LOW-level output voltage VOL 0.25 0.6 V VI = VIH or VIL; IO = 18 mA; VCC = 2.3 V 4
LOW-level output voltage VOL 0.16 0.4 V VI = VIH or VIL; IO = 12 mA; VCC = 2.7 V 4
LOW-level output voltage VOL 0.23 0.45 V VI = VIH or VIL; IO = 18 mA; VCC = 3.0 V 4
LOW-level output voltage VOL 0.3 0.55 V VI = VIH or VIL; IO = 24 mA; VCC = 3.0 V 4
input leakage current II -20 20 μA VCC = 3.6 V; VI = 3.6 V or GND 4
power-off leakage current IOFF -80 80 μA VCC = 0 V; VI or VO = 0 V to 3.6 V 4
supply current ICC 0.2 80 μA VCC = 3.6 V; VI = VCC or GND; IO = 0 A 4
additional supply current ΔICC 5 750 μA per input pin; VCC = 3.0 V to 3.6 V; VI = VCC - 0.6 V; IO = 0 A 4
propagation delay tpd 1 2.8 5.4 ns nA, nB to nY; VCC = 1.65 V to 1.95 V 5
propagation delay tpd 1 2 3.6 ns nA, nB to nY; VCC = 2.3 V to 2.7 V 5
propagation delay tpd 1 2.2 3.3 ns nA, nB to nY; VCC = 2.7 V 5
propagation delay tpd 1 2 3.2 ns nA, nB to nY; VCC = 3.0 V to 3.6 V 5
input capacitance CI 3.5 pF 4
power dissipation capacitance CPD 25 pF per gate; VI = GND to VCC; VCC = 3.3 V 5

CAD (KiCad official)

  • Symbol: 74ALVC32PW
  • Footprint: Package_SO:TSSOP-14_4.4x5mm_P0.65mm
  • 3D model: TSSOP-14 (KiCad packages3D, STEP)
  • 3D model files: 74alvc32pw-etched.step / 74alvc32pw-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); 74alvc32pw.step / 74alvc32pw.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Nexperia datasheet (12 pp, sha256 8c9f20060d9831e4, retrieved 2026-10-20, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus off (skipped (clean text read)), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF