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Name	Last commit message	Last updated
docs	74alvc02pw: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray	1mo ago
viewers	74alvc02pw: viewers · Ray	1mo ago
74alvc02pw-etched.fit.json	74alvc02pw: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray	1mo ago
74alvc02pw-etched.glb	74alvc02pw: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray	1mo ago
74alvc02pw-etched.step	74alvc02pw: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray	1mo ago
74alvc02pw.glb	Publish 0.1.0 · Ray	1mo ago
74alvc02pw.kicad_mod	Publish 0.1.0 · Ray	1mo ago
74alvc02pw.kicad_sym	Publish 0.1.0 · Ray	1mo ago
74alvc02pw.lbr	Publish 0.1.0 · Ray	1mo ago
74alvc02pw.step	Publish 0.1.0 · Ray	1mo ago
package.json	Publish 0.1.0 · Ray	1mo ago
page.json	74alvc02pw: component.models_3d pose record per STEP (Z-up, seated z=0, pad-centre origin, identity binding) · Ray	27d ago
README.md	74alvc02pw: laser-etched CAD + chip hero (factory 2.0.0 backfill) · Ray	1mo ago

74ALVC02PW

Nexperia · Logic Gates · TSSOP-14

74ALVC02PW from Nexperia, in a TSSOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	1Y	output	Data output of NOR gate 1. Logic HIGH only when both inputs 1A and 1B are LOW. Output drive up to 24 mA at VCC = 3.0 V.
2	1A	input	Data input A of NOR gate 1. Schmitt trigger input, overvoltage tolerant to 3.6 V. Input leakage current ±5 µA typ.
3	1B	input	Data input B of NOR gate 1. Schmitt trigger input, overvoltage tolerant to 3.6 V.
4	2Y	output	Data output of NOR gate 2. Logic HIGH only when both inputs 2A and 2B are LOW. Output drive up to 24 mA at VCC = 3.0 V.
5	2A	input	Data input A of NOR gate 2. Schmitt trigger input, overvoltage tolerant to 3.6 V.
6	2B	input	Data input B of NOR gate 2. Schmitt trigger input, overvoltage tolerant to 3.6 V.
7	GND	power_in	Ground reference (0 V). Ground current IGND rated to -100 mA.
8	3A	input	Data input A of NOR gate 3. Schmitt trigger input, overvoltage tolerant to 3.6 V.
9	3B	input	Data input B of NOR gate 3. Schmitt trigger input, overvoltage tolerant to 3.6 V.
10	3Y	output	Data output of NOR gate 3. Logic HIGH only when both inputs 3A and 3B are LOW. Output drive up to 24 mA at VCC = 3.0 V.
11	4A	input	Data input A of NOR gate 4. Schmitt trigger input, overvoltage tolerant to 3.6 V.
12	4B	input	Data input B of NOR gate 4. Schmitt trigger input, overvoltage tolerant to 3.6 V.
13	4Y	output	Data output of NOR gate 4. Logic HIGH only when both inputs 4A and 4B are LOW. Output drive up to 24 mA at VCC = 3.0 V.
14	VCC	power_in	Supply voltage input. Operating range 1.65 V to 3.6 V; absolute maximum -0.5 V to +4.6 V. Supply current ICC ≤ 20 µA typ.

Key specifications

Parameter	Value
Manufacturer	Nexperia
Package	TSSOP-14
Category	Logic
Pins	14

Ordering variants

Same part, different packaging or reel option.

74ALVC02PW
74ALVC02PWD
74ALVC02PWBQ

CAD (KiCad official)

Symbol: 74ALVC02PW
Footprint: Package_SO:TSSOP-14_4.4x5mm_P0.65mm
3D model: TSSOP-14 (KiCad packages3D, STEP)
3D model files: 74alvc02pw-etched.step / 74alvc02pw-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); 74alvc02pw.step / 74alvc02pw.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Nexperia datasheet (12 pp, sha256 19d430faa98000fc, retrieved 2026-08-17, tier: manufacturer)
Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF