component
74ALVC02D
Public Made by Adomby adom
Nexperia Logic Gates, SO-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by adom_assets · KiCad file format 20240108
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74ALVC02D
Nexperia · Logic Gates · SO-14
74ALVC02D from Nexperia, in a SO-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1Y | output | Data output of gate 1 (NOR of 1A and 1B), which swings between GND and VCC. |
| 2 | 1A | input | Data input of gate 1; overvoltage tolerant to 3.6 V with Schmitt-trigger action that tolerates slow rise and fall times. |
| 3 | 1B | input | Data input of gate 1; overvoltage tolerant to 3.6 V with Schmitt-trigger action that tolerates slow rise and fall times. |
| 4 | 2Y | output | Data output of gate 2 (NOR of 2A and 2B), which swings between GND and VCC. |
| 5 | 2A | input | Data input of gate 2; overvoltage tolerant to 3.6 V with Schmitt-trigger action that tolerates slow rise and fall times. |
| 6 | 2B | input | Data input of gate 2; overvoltage tolerant to 3.6 V with Schmitt-trigger action that tolerates slow rise and fall times. |
| 7 | GND | power_in | Ground reference (0 V) for all voltages in the datasheet. |
| 8 | 3A | input | Data input of gate 3; overvoltage tolerant to 3.6 V with Schmitt-trigger action that tolerates slow rise and fall times. |
| 9 | 3B | input | Data input of gate 3; overvoltage tolerant to 3.6 V with Schmitt-trigger action that tolerates slow rise and fall times. |
| 10 | 3Y | output | Data output of gate 3 (NOR of 3A and 3B), which swings between GND and VCC. |
| 11 | 4A | input | Data input of gate 4; overvoltage tolerant to 3.6 V with Schmitt-trigger action that tolerates slow rise and fall times. |
| 12 | 4B | input | Data input of gate 4; overvoltage tolerant to 3.6 V with Schmitt-trigger action that tolerates slow rise and fall times. |
| 13 | 4Y | output | Data output of gate 4 (NOR of 4A and 4B), which swings between GND and VCC. |
| 14 | VCC | power_in | Supply voltage, recommended range 1.65 V to 3.6 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Nexperia |
| Package | SO-14 |
| Category | Logic |
| Pins | 14 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage (recommended operating) | VCC | 1.65 | 3.6 | V | 3 | ||
| Input voltage (recommended operating) | VI | 0 | 3.6 | V | 3 | ||
| Output voltage (recommended operating) | VO | 0 | V | VCC = 1.65 to 3.6 V | 3 | ||
| Output voltage (recommended operating, power-down) | VO | 0 | 3.6 | V | power-down mode; VCC = 0 V | 3 | |
| Ambient temperature | Tamb | -40 | 125 | °C | 3 | ||
| Input transition rise and fall rate | Δt/ΔV | 0 | 20 | ns/V | VCC = 1.65 V to 2.7 V | 3 | |
| Input transition rise and fall rate | Δt/ΔV | 0 | 10 | ns/V | VCC = 2.7 V to 3.6 V | 3 | |
| Supply voltage (absolute maximum) | VCC | -0.5 | 4.6 | V | 3 | ||
| Input voltage (absolute maximum) | VI | -0.5 | 4.6 | V | 3 | ||
| Output voltage (absolute maximum) | VO | -0.5 | V | output HIGH or LOW state | 3 | ||
| Output voltage (absolute maximum, power-down) | VO | -0.5 | 4.6 | V | power-down mode; VCC = 0 V | 3 | |
| Input clamping current | IIK | -50 | mA | VI < 0 V | 3 | ||
| Output clamping current | IOK | -50 | 50 | mA | VO > VCC or VO < 0 V | 3 | |
| Output current | IO | -50 | 50 | mA | VO = 0 V to VCC | 3 | |
| Supply current | ICC | 100 | mA | 3 | |||
| Ground current | IGND | -100 | mA | 3 | |||
| Storage temperature | Tstg | -65 | 150 | °C | 3 | ||
| Total power dissipation | Ptot | 500 | mW | Tamb = -40 °C to +125 °C | 3 | ||
| HIGH-level input voltage | VIH | 1.7 | V | VCC = 2.3 V to 2.7 V | 4 | ||
| HIGH-level input voltage | VIH | 2 | V | VCC = 2.7 V to 3.6 V | 4 | ||
| LOW-level input voltage | VIL | 0.7 | V | VCC = 2.3 V to 2.7 V | 4 | ||
| LOW-level input voltage | VIL | 0.8 | V | VCC = 2.7 V to 3.6 V | 4 | ||
| HIGH-level output voltage | VOH | 1.25 | 1.51 | V | VI = VIH or VIL; IO = -6 mA; VCC = 1.65 V | 4 | |
| HIGH-level output voltage | VOH | 1.8 | 2.1 | V | VI = VIH or VIL; IO = -12 mA; VCC = 2.3 V | 4 | |
| HIGH-level output voltage | VOH | 1.7 | 2.01 | V | VI = VIH or VIL; IO = -18 mA; VCC = 2.3 V | 4 | |
| HIGH-level output voltage | VOH | 2.2 | 2.53 | V | VI = VIH or VIL; IO = -12 mA; VCC = 2.7 V | 4 | |
| HIGH-level output voltage | VOH | 2.4 | 2.76 | V | VI = VIH or VIL; IO = -18 mA; VCC = 3.0 V | 4 | |
| HIGH-level output voltage | VOH | 2.2 | 2.68 | V | VI = VIH or VIL; IO = -24 mA; VCC = 3.0 V | 4 | |
| LOW-level output voltage | VOL | 0.2 | V | VI = VIH or VIL; IO = 100 μA; VCC = 1.65 V to 3.6 V | 4 | ||
| LOW-level output voltage | VOL | 0.11 | 0.3 | V | VI = VIH or VIL; IO = 6 mA; VCC = 1.65 V | 4 | |
| LOW-level output voltage | VOL | 0.17 | 0.4 | V | VI = VIH or VIL; IO = 12 mA; VCC = 2.3 V | 4 | |
| LOW-level output voltage | VOL | 0.25 | 0.6 | V | VI = VIH or VIL; IO = 18 mA; VCC = 2.3 V | 4 | |
| LOW-level output voltage | VOL | 0.16 | 0.4 | V | VI = VIH or VIL; IO = 12 mA; VCC = 2.7 V | 4 | |
| LOW-level output voltage | VOL | 0.23 | 0.45 | V | VI = VIH or VIL; IO = 18 mA; VCC = 3.0 V | 4 | |
| LOW-level output voltage | VOL | 0.3 | 0.55 | V | VI = VIH or VIL; IO = 24 mA; VCC = 3.0 V | 4 | |
| Input leakage current | II | -20 | 0.1 | 20 | μA | VCC = 3.6 V; VI = 3.6 V or GND | 4 |
| Power-off leakage current | IOFF | -80 | 0.1 | 80 | μA | VCC = 0 V; VI or VO = 0 V to 3.6 V | 4 |
| Supply current | ICC | 0.2 | 160 | μA | VCC = 3.6 V; VI = VCC or GND; IO = 0 A | 4 | |
| Additional supply current | ΔICC | 5 | 750 | μA | per input pin; VCC = 3.0 V to 3.6 V; VI = VCC - 0.6 V; IO = 0 A | 4 | |
| Propagation delay nA, nB to nY | tpd | 1 | 2.8 | 5.4 | ns | nA, nB to nY; see Fig. 4; VCC = 1.65 V to 1.95 V | 5 |
| Propagation delay nA, nB to nY | tpd | 1 | 2 | 3.6 | ns | nA, nB to nY; see Fig. 4; VCC = 2.3 V to 2.7 V | 5 |
| Propagation delay nA, nB to nY | tpd | 1 | 2.5 | 3.6 | ns | nA, nB to nY; see Fig. 4; VCC = 2.7 V | 5 |
| Propagation delay nA, nB to nY | tpd | 1 | 2.2 | 3.2 | ns | nA, nB to nY; see Fig. 4; VCC = 3.0 V to 3.6 V | 5 |
CAD (KiCad official)
- Symbol:
74ALVC02D - Footprint:
Adom_Gen:Nexperia_74 - 3D model: SO-14 (KiCad packages3D, STEP)
- 3D model files:
74alvc02d-etched.step/74alvc02d-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);74alvc02d.step/74alvc02d.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Nexperia datasheet (12 pp, sha256
19d430faa98000fc, retrieved 2026-10-18, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).