# 74AHCT74PW

**Nexperia** · Flip Flops · TSSOP-14

74AHCT74PW from Nexperia, in a TSSOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1RD | input | Asynchronous reset direct input (active LOW) that operates independent of the clock input. |
| 2 | 1D | input | Data input, transferred to 1Q on the LOW to HIGH clock transition, with set-up time required before the clock edge. |
| 3 | 1CP | input | Clock input, edge-triggered on the LOW to HIGH transition, with Schmitt-trigger action that tolerates slow rise and fall times. |
| 4 | 1SD | input | Asynchronous set direct input (active LOW) that operates independent of the clock input. |
| 5 | 1Q | output | True flip-flop output. |
| 6 | 1Q | output | Complement flip-flop output. |
| 7 | GND | power_in | Ground (0 V) reference for all voltages on the device. |
| 8 | 2Q | output | Complement flip-flop output. |
| 9 | 2Q | output | True flip-flop output. |
| 10 | 2SD | input | Asynchronous set direct input (active LOW) that operates independent of the clock input. |
| 11 | 2CP | input | Clock input, edge-triggered on the LOW to HIGH transition, with Schmitt-trigger action that tolerates slow rise and fall times. |
| 12 | 2D | input | Data input, transferred to 2Q on the LOW to HIGH clock transition, with set-up time required before the clock edge. |
| 13 | 2RD | input | Asynchronous reset direct input (active LOW) that operates independent of the clock input. |
| 14 | VCC | power_in | Supply voltage: 2.0 V to 5.5 V for 74AHC74 and 4.5 V to 5.5 V for 74AHCT74 per the recommended operating conditions. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Nexperia |
| Package | TSSOP-14 |
| Category | Logic |
| Pins | 14 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage | VCC | -0.5 |  | 7 | V |  | 4 |
| Input voltage | VI | -0.5 |  | 7 | V |  | 4 |
| Input clamping current | IIK | -20 |  |  | mA | VI < -0.5 V | 4 |
| Output clamping current | IOK | -20 |  | 20 | mA | VO < -0.5 V or VO > VCC + 0.5 V | 4 |
| Output current | IO | -25 |  | 25 | mA | VO = -0.5 V to (VCC + 0.5 V) | 4 |
| Supply current | ICC |  |  | 75 | mA |  | 4 |
| Ground current | IGND | -75 |  |  | mA |  | 4 |
| Storage temperature | Tstg | -65 |  | 150 | °C |  | 4 |
| Total power dissipation | Ptot |  |  | 500 | mW | Tamb = -40 °C to +125 °C | 4 |
| Supply voltage | VCC | 4.5 | 5 | 5.5 | V |  | 4 |
| Input voltage | VI | 0 |  | 5.5 | V |  | 4 |
| Output voltage | VO | 0 |  |  | V |  | 4 |
| Ambient temperature | Tamb | -40 | 25 | 125 | °C |  | 4 |
| Input transition rise and fall rate | Δt/ΔV |  |  | 20 | ns/V | VCC = 4.5 V to 5.5 V | 4 |
| HIGH-level input voltage | VIH | 2 |  |  | V | VCC = 4.5 V to 5.5 V | 5 |
| LOW-level input voltage | VIL |  |  | 0.8 | V | VCC = 4.5 V to 5.5 V | 5 |
| HIGH-level output voltage | VOH | 4.4 | 4.5 |  | V | VI = VIH or VIL; VCC = 4.5 V; IO = -50 μA | 5 |
| HIGH-level output voltage | VOH | 4.4 |  |  | V | -40 °C to +125 °C; VI = VIH or VIL; VCC = 4.5 V; IO = -50 μA | 5 |
| HIGH-level output voltage | VOH | 3.94 |  |  | V | VI = VIH or VIL; VCC = 4.5 V; IO = -8.0 mA | 5 |
| HIGH-level output voltage | VOH | 3.7 |  |  | V | -40 °C to +125 °C; VI = VIH or VIL; VCC = 4.5 V; IO = -8.0 mA | 5 |
| LOW-level output voltage | VOL |  | 0 | 0.1 | V | VI = VIH or VIL; VCC = 4.5 V; IO = 50 μA | 5 |
| LOW-level output voltage | VOL |  |  | 0.1 | V | -40 °C to +125 °C; VI = VIH or VIL; VCC = 4.5 V; IO = 50 μA | 5 |
| LOW-level output voltage | VOL |  |  | 0.36 | V | VI = VIH or VIL; VCC = 4.5 V; IO = 8.0 mA | 5 |
| LOW-level output voltage | VOL |  |  | 0.55 | V | -40 °C to +125 °C; VI = VIH or VIL; VCC = 4.5 V; IO = 8.0 mA | 5 |
| Input leakage current | II |  |  | 0.1 | μA | VI = 5.5 V or GND; VCC = 0 V to 5.5 V | 5 |
| Input leakage current | II |  |  | 2 | μA | -40 °C to +125 °C; VI = 5.5 V or GND; VCC = 0 V to 5.5 V | 5 |
| Supply current | ICC |  |  | 2 | μA | VI = VCC or GND; IO = 0 A; VCC = 5.5 V | 5 |
| Supply current | ICC |  |  | 40 | μA | -40 °C to +125 °C; VI = VCC or GND; IO = 0 A; VCC = 5.5 V | 5 |
| Additional supply current | ΔICC |  |  | 1.35 | mA | per input pin; VI = VCC - 2.1 V; other pins at VCC or GND; IO = 0 A; VCC = 4.5 V to 5.5 V | 6 |
| Input capacitance | CI |  | 3 | 10 | pF | VI = VCC or GND | 6 |
| Propagation delay nCP to nQ, nQ | tpd |  | 3.3 | 7.8 | ns | VCC = 4.5 V to 5.5 V; CL = 15 pF; see Fig. 5 | 7 |
| Propagation delay nCP to nQ, nQ | tpd | 1 |  | 10 | ns | -40 °C to +125 °C; VCC = 4.5 V to 5.5 V; CL = 15 pF; see Fig. 5 | 7 |
| Propagation delay nCP to nQ, nQ | tpd |  | 4.8 | 8.8 | ns | VCC = 4.5 V to 5.5 V; CL = 50 pF; see Fig. 5 | 7 |
| Propagation delay nCP to nQ, nQ | tpd | 1 |  | 11 | ns | -40 °C to +125 °C; VCC = 4.5 V to 5.5 V; CL = 50 pF; see Fig. 5 | 7 |
| Propagation delay nSD, nRD to nQ, nQ | tpd |  | 3.7 | 10.4 | ns | VCC = 4.5 V to 5.5 V; CL = 15 pF; see Fig. 5 | 7 |
| Propagation delay nSD, nRD to nQ, nQ | tpd | 1 |  | 13 | ns | -40 °C to +125 °C; VCC = 4.5 V to 5.5 V; CL = 15 pF; see Fig. 5 | 7 |
| Propagation delay nSD, nRD to nQ, nQ | tpd |  | 5.3 | 11.4 | ns | VCC = 4.5 V to 5.5 V; CL = 50 pF; see Fig. 5 | 7 |
| Propagation delay nSD, nRD to nQ, nQ | tpd | 1 |  | 14.5 | ns | -40 °C to +125 °C; VCC = 4.5 V to 5.5 V; CL = 50 pF; see Fig. 5 | 7 |
| Maximum frequency | fmax | 100 | 160 |  | MHz | VCC = 4.5 V to 5.5 V; CL = 15 pF; see Fig. 5 | 7 |
| Maximum frequency | fmax | 80 |  |  | MHz | -40 °C to +125 °C; VCC = 4.5 V to 5.5 V; CL = 15 pF; see Fig. 5 | 7 |
| Maximum frequency | fmax | 80 | 140 |  | MHz | VCC = 4.5 V to 5.5 V; CL = 50 pF; see Fig. 5 | 7 |
| Maximum frequency | fmax | 65 |  |  | MHz | -40 °C to +125 °C; VCC = 4.5 V to 5.5 V; CL = 50 pF; see Fig. 5 | 7 |
| Pulse width | tW | 5 |  |  | ns | CP HIGH or LOW; nSD, nRD LOW; VCC = 4.5 V to 5.5 V; see Fig. 5 and Fig. 6 | 7 |
| Set-up time | tsu | 5 |  |  | ns | nD to nCP; VCC = 4.5 V to 5.5 V; see Fig. 5 | 7 |
| Hold time | th | 0 |  |  | ns | nD to nCP; VCC = 4.5 V to 5.5 V; see Fig. 5 | 7 |
| Recovery time | trec | 3.5 |  |  | ns | nRD to nCP; VCC = 4.5 V to 5.5 V; see Fig. 6 | 7 |
| Power dissipation capacitance | CPD |  | 16 |  | pF | fi = 1 MHz; VI = GND to VCC | 7 |

## CAD (KiCad official)

- Symbol: `74AHCT74PW`
- Footprint: `Package_SO:TSSOP-14_4.4x5mm_P0.65mm`
- 3D model: TSSOP-14 (KiCad packages3D, STEP)
- 3D model files: `74ahct74pw-etched.step` / `74ahct74pw-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `74ahct74pw.step` / `74ahct74pw.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Nexperia datasheet](https://assets.nexperia.com/documents/data-sheet/74AHCT74PW.pdf) (15 pp, sha256 `16494543b3aab84c`, retrieved 2026-10-21, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `off` (skipped (clean text read)), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/74ahct74pw-datasheet.pdf)