component
74AHCT74D
Public Made by Adomby adom
Nexperia Flip Flops, SOIC-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
Open in new tab ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.
Symbol & Footprint
Schematic Symbol
Open full view ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
PCB Footprint
Open full view ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
Datasheet
Open in new tab ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
README
markdown74AHCT74D
Nexperia · Flip Flops · SOIC-14
74AHCT74D from Nexperia, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1RD | input | Asynchronous reset direct input for flip-flop 1, active LOW, operating independently of the clock input. |
| 2 | 1D | input | Data input for flip-flop 1, transferred to 1Q on the LOW to HIGH clock transition; must be stable one set-up time before that transition. |
| 3 | 1CP | input | Clock input for flip-flop 1, edge-triggered on the LOW to HIGH transition, with Schmitt-trigger action for slow clock edges. |
| 4 | 1SD | input | Asynchronous set direct input for flip-flop 1, active LOW, operating independently of the clock input. |
| 5 | 1Q | output | True flip-flop output of flip-flop 1. |
| 6 | 1Q | output | Complement flip-flop output of flip-flop 1. |
| 7 | GND | power_in | Ground (0 V) reference for all voltages. |
| 8 | 2Q | output | Complement flip-flop output of flip-flop 2. |
| 9 | 2Q | output | True flip-flop output of flip-flop 2. |
| 10 | 2SD | input | Asynchronous set direct input for flip-flop 2, active LOW, operating independently of the clock input. |
| 11 | 2CP | input | Clock input for flip-flop 2, edge-triggered on the LOW to HIGH transition, with Schmitt-trigger action for slow clock edges. |
| 12 | 2D | input | Data input for flip-flop 2, transferred to 2Q on the LOW to HIGH clock transition; must be stable one set-up time before that transition. |
| 13 | 2RD | input | Asynchronous reset direct input for flip-flop 2, active LOW, operating independently of the clock input. |
| 14 | VCC | power_in | Supply voltage; recommended 2.0 V to 5.5 V for 74AHC74 and 4.5 V to 5.5 V for 74AHCT74. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Nexperia |
| Package | SOIC-14 |
| Category | Logic |
| Pins | 14 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| supply voltage | VCC | 4.5 | 5 | 5.5 | V | 4 | |
| input voltage | VI | 0 | 5.5 | V | 4 | ||
| output voltage | VO | 0 | V | maximum printed as VCC | 4 | ||
| ambient temperature | Tamb | -40 | 25 | 125 | °C | 4 | |
| input transition rise and fall rate | Δt/ΔV | 20 | ns/V | VCC = 4.5 V to 5.5 V | 4 | ||
| supply voltage | VCC | -0.5 | 7 | V | 4 | ||
| input voltage | VI | -0.5 | 7 | V | 4 | ||
| input clamping current | IIK | -20 | mA | VI < -0.5 V | 4 | ||
| output clamping current | IOK | -20 | 20 | mA | VO < -0.5 V or VO > VCC + 0.5 V | 4 | |
| output current | IO | -25 | 25 | mA | VO = -0.5 V to (VCC + 0.5 V) | 4 | |
| supply current | ICC | 75 | mA | 4 | |||
| ground current | IGND | -75 | mA | 4 | |||
| storage temperature | Tstg | -65 | 150 | °C | 4 | ||
| total power dissipation | Ptot | 500 | mW | Tamb = -40 °C to +125 °C | 4 | ||
| HIGH-level input voltage | VIH | 2 | V | VCC = 4.5 V to 5.5 V; 25 °C | 5 | ||
| LOW-level input voltage | VIL | 0.8 | V | VCC = 4.5 V to 5.5 V; 25 °C | 5 | ||
| HIGH-level output voltage | VOH | 4.4 | 4.5 | V | VI = VIH or VIL; VCC = 4.5 V; IO = -50 μA; 25 °C | 5 | |
| HIGH-level output voltage | VOH | 3.94 | V | VI = VIH or VIL; VCC = 4.5 V; IO = -8.0 mA; 25 °C | 5 | ||
| HIGH-level output voltage | VOH | 3.7 | V | VI = VIH or VIL; VCC = 4.5 V; IO = -8.0 mA; -40 °C to +125 °C | 5 | ||
| LOW-level output voltage | VOL | 0 | 0.1 | V | VI = VIH or VIL; VCC = 4.5 V; IO = 50 μA; 25 °C | 5 | |
| LOW-level output voltage | VOL | 0.36 | V | VI = VIH or VIL; VCC = 4.5 V; IO = 8.0 mA; 25 °C | 5 | ||
| LOW-level output voltage | VOL | 0.55 | V | VI = VIH or VIL; VCC = 4.5 V; IO = 8.0 mA; -40 °C to +125 °C | 5 | ||
| input leakage current | II | 0.1 | μA | VI = 5.5 V or GND; VCC = 0 V to 5.5 V; 25 °C | 5 | ||
| input leakage current | II | 2 | μA | VI = 5.5 V or GND; VCC = 0 V to 5.5 V; -40 °C to +125 °C | 5 | ||
| supply current | ICC | 2 | μA | VI = VCC or GND; IO = 0 A; VCC = 5.5 V; 25 °C | 5 | ||
| supply current | ICC | 40 | μA | VI = VCC or GND; IO = 0 A; VCC = 5.5 V; -40 °C to +125 °C | 5 | ||
| additional supply current | ΔICC | 1.35 | mA | per input pin; VI = VCC - 2.1 V; other pins at VCC or GND; IO = 0 A; VCC = 4.5 V to 5.5 V; 25 °C | 6 | ||
| additional supply current | ΔICC | 1.5 | mA | per input pin; VI = VCC - 2.1 V; other pins at VCC or GND; IO = 0 A; VCC = 4.5 V to 5.5 V; -40 °C to +125 °C | 6 | ||
| input capacitance | CI | 3 | 10 | pF | VI = VCC or GND; 25 °C | 6 | |
| input capacitance | CI | 10 | pF | VI = VCC or GND; -40 °C to +125 °C | 6 | ||
| propagation delay nCP to nQ, nQ | tpd | 3.3 | 7.8 | ns | VCC = 4.5 V to 5.5 V; CL = 15 pF; see Fig. 5; 25 °C | 7 | |
| propagation delay nCP to nQ, nQ | tpd | 1 | 10 | ns | VCC = 4.5 V to 5.5 V; CL = 15 pF; see Fig. 5; -40 °C to +125 °C | 7 | |
| propagation delay nCP to nQ, nQ | tpd | 4.8 | 8.8 | ns | VCC = 4.5 V to 5.5 V; CL = 50 pF; see Fig. 5; 25 °C | 7 | |
| propagation delay nCP to nQ, nQ | tpd | 1 | 11 | ns | VCC = 4.5 V to 5.5 V; CL = 50 pF; see Fig. 5; -40 °C to +125 °C | 7 | |
| propagation delay nSD, nRD to nQ, nQ | tpd | 3.7 | 10.4 | ns | VCC = 4.5 V to 5.5 V; CL = 15 pF; see Fig. 6; 25 °C | 7 | |
| propagation delay nSD, nRD to nQ, nQ | tpd | 1 | 13 | ns | VCC = 4.5 V to 5.5 V; CL = 15 pF; see Fig. 6; -40 °C to +125 °C | 7 | |
| propagation delay nSD, nRD to nQ, nQ | tpd | 5.3 | 11.4 | ns | VCC = 4.5 V to 5.5 V; CL = 50 pF; see Fig. 5; 25 °C | 7 | |
| propagation delay nSD, nRD to nQ, nQ | tpd | 1 | 14.5 | ns | VCC = 4.5 V to 5.5 V; CL = 50 pF; see Fig. 5; -40 °C to +125 °C | 7 | |
| maximum frequency | fmax | 100 | 160 | MHz | VCC = 4.5 V to 5.5 V; CL = 15 pF; see Fig. 5; 25 °C | 7 | |
| maximum frequency | fmax | 80 | MHz | VCC = 4.5 V to 5.5 V; CL = 15 pF; see Fig. 5; -40 °C to +125 °C | 7 | ||
| maximum frequency | fmax | 80 | 140 | MHz | VCC = 4.5 V to 5.5 V; CL = 50 pF; see Fig. 5; 25 °C | 7 | |
| maximum frequency | fmax | 65 | MHz | VCC = 4.5 V to 5.5 V; CL = 50 pF; see Fig. 5; -40 °C to +125 °C | 7 | ||
| pulse width | tW | 5 | ns | VCC = 4.5 V to 5.5 V; CP HIGH or LOW; nSD, nRD LOW; see Fig. 5 and Fig. 6; 25 °C | 7 | ||
| set-up time | tsu | 5 | ns | nD to nCP; VCC = 4.5 V to 5.5 V; see Fig. 5; 25 °C | 7 | ||
| hold time | th | 0 | ns | nD to nCP; VCC = 4.5 V to 5.5 V; see Fig. 5; 25 °C | 7 | ||
| recovery time | trec | 3.5 | ns | nRD to nCP; VCC = 4.5 V to 5.5 V; see Fig. 6; 25 °C | 7 | ||
| power dissipation capacitance | CPD | 16 | pF | fi = 1 MHz; VI = GND to VCC | 7 |
CAD (KiCad official)
- Symbol:
74AHCT74D - Footprint:
Package_SO:SOIC-14_3.9x8.7mm_P1.27mm - 3D model: SOIC-14 (KiCad packages3D, STEP)
- 3D model files:
74ahct74d-etched.step/74ahct74d-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);74ahct74d.step/74ahct74d.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Nexperia datasheet (15 pp, sha256
16494543b3aab84c, retrieved 2026-10-27, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusoff(skipped (clean text read)), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).