74AHCT594PW

{
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  "type": "component",
  "slug": "74ahct594pw",
  "title": "74AHCT594PW",
  "brief": "Nexperia Shift Registers, TSSOP-16. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.",
  "version": "0.1.0",
  "license": "CC-BY-SA-4.0",
  "tags": [
    "component",
    "logic",
    "74ahct594pw"
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  "component": {
    "mpn": "74AHCT594PW",
    "manufacturer": "Nexperia",
    "package": "TSSOP-16",
    "pin_count": 16,
    "category": "Logic",
    "subcategory": "Shift Registers",
    "datasheet": "https://assets.nexperia.com/documents/data-sheet/74AHCT594PW.pdf",
    "parts": {
      "symbol": "74ahct594pw.kicad_sym",
      "footprint": "74ahct594pw.kicad_mod",
      "model_3d": "74ahct594pw-etched.glb",
      "model_3d_plain": "74ahct594pw.glb",
      "model_3d_step": "74ahct594pw-etched.step",
      "model_3d_step_plain": "74ahct594pw.step",
      "lbr": "74ahct594pw.lbr"
    },
    "distributor_links": {},
    "pins": [
      {
        "number": "1",
        "name": "Q1",
        "type": "output",
        "description": "Parallel data output bit 1 from the 8-bit storage register. CMOS push-pull output; drive capability up to 8 mA at VCC = 4.5 V (VOL ≤ 0.44 V)."
      },
      {
        "number": "2",
        "name": "Q2",
        "type": "output",
        "description": "Parallel data output bit 2 from the 8-bit storage register. CMOS push-pull output; drive capability up to 8 mA at VCC = 4.5 V."
      },
      {
        "number": "3",
        "name": "Q3",
        "type": "output",
        "description": "Parallel data output bit 3 from the 8-bit storage register. CMOS push-pull output; drive capability up to 8 mA at VCC = 4.5 V."
      },
      {
        "number": "4",
        "name": "Q4",
        "type": "output",
        "description": "Parallel data output bit 4 from the 8-bit storage register. CMOS push-pull output; drive capability up to 8 mA at VCC = 4.5 V."
      },
      {
        "number": "5",
        "name": "Q5",
        "type": "output",
        "description": "Parallel data output bit 5 from the 8-bit storage register. CMOS push-pull output; drive capability up to 8 mA at VCC = 4.5 V."
      },
      {
        "number": "6",
        "name": "Q6",
        "type": "output",
        "description": "Parallel data output bit 6 from the 8-bit storage register. CMOS push-pull output; drive capability up to 8 mA at VCC = 4.5 V."
      },
      {
        "number": "7",
        "name": "Q7",
        "type": "output",
        "description": "Parallel data output bit 7 (MSB) from the 8-bit storage register. CMOS push-pull output; drive capability up to 8 mA at VCC = 4.5 V."
      },
      {
        "number": "8",
        "name": "GND",
        "type": "power_in",
        "description": "Ground reference (0 V). Maximum ground current 75 mA."
      },
      {
        "number": "9",
        "name": "Q7S",
        "type": "output",
        "description": "Serial data output - the last stage of the shift register (before the storage latch). Used for cascading additional 74AHCT594 devices; changes on rising edge of SHCP."
      },
      {
        "number": "10",
        "name": "SHR",
        "type": "input",
        "description": "Shift-register reset input, active LOW (asynchronous). Driving SHR LOW clears the internal 8-bit shift register only; the storage register is unaffected. Schmitt-trigger TTL-compatible input, overvoltage tolerant to 5.5 V."
      },
      {
        "number": "11",
        "name": "SHCP",
        "type": "input",
        "description": "Shift-register clock input. Data on DS is shifted into the shift register on the LOW-to-HIGH transition. Schmitt-trigger TTL-compatible input; fmax ≥ 70 MHz at VCC = 4.5 V-5.5 V."
      },
      {
        "number": "12",
        "name": "STCP",
        "type": "input",
        "description": "Storage-register clock input. On the LOW-to-HIGH transition, the contents of the shift register are latched into the 8-bit storage register and appear on Q0-Q7. Schmitt-trigger TTL-compatible input."
      },
      {
        "number": "13",
        "name": "STR",
        "type": "input",
        "description": "Storage-register reset input, active LOW (asynchronous). Driving STR LOW forces all parallel outputs Q0-Q7 LOW; the shift register is unaffected. Schmitt-trigger TTL-compatible input, overvoltage tolerant to 5.5 V."
      },
      {
        "number": "14",
        "name": "DS",
        "type": "input",
        "description": "Serial data input to the shift register. Sampled on the LOW-to-HIGH transition of SHCP. tsu = 3 ns, th = 2 ns (VCC = 4.5 V). Schmitt-trigger TTL-compatible input."
      },
      {
        "number": "15",
        "name": "Q0",
        "type": "output",
        "description": "Parallel data output bit 0 (LSB) from the 8-bit storage register. CMOS push-pull output; drive capability up to 8 mA at VCC = 4.5 V."
      },
      {
        "number": "16",
        "name": "VCC",
        "type": "power_in",
        "description": "Positive supply voltage. Operating range 4.5 V to 5.5 V for the 74AHCT594 (TTL-level inputs). Absolute maximum 7.0 V."
      }
    ],
    "provenance": {
      "extractor": "ds2sf",
      "datasheet": {
        "url": "https://assets.nexperia.com/documents/data-sheet/74AHCT594PW.pdf",
        "pages": 19,
        "sha256": "904f218d5c3a23ea",
        "source_tier": "mfr"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 16,
        "described": 16,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
    },
    "viewers": {
      "symbol": "viewers/symbol.html",
      "footprint": "viewers/footprint.html"
    },
    "logic": {
      "family_id": "74AHCT594",
      "logic_family": "74AHCT",
      "function_code": "594",
      "function_class": null,
      "function_name": null,
      "manufacturer": null,
      "is_specialty": false
    },
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        "role": "plain",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          6.4,
          5.0,
          1.1
        ],
        "zmin_mm": -0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "6ad5e98224d02a427d9a6b929a28dbc158b9925fba5adec12db05079f1016948",
        "checked": "2026-10-07",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      },
      {
        "file": "74ahct594pw-etched.step",
        "role": "eda",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
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        "zmin_mm": -0.0,
        "centre_offset_mm": 0.0,
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        "sha256": "1b052f6dc962634d35ba1c731d29a9955b43f6763634711d22265a536578a267",
        "checked": "2026-10-07",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      }
    ]
  },
  "metadata": {
    "specs": {
      "Manufacturer": "Nexperia",
      "Package": "TSSOP-16",
      "Category": "Logic",
      "Pins": "16"
    }
  },
  "variants": [
    {
      "mpn": "74AHCT594PW",
      "kind": "packaging"
    },
    {
      "mpn": "74AHCT594PWD",
      "kind": "packaging"
    },
    {
      "mpn": "74AHCT594PWBQ",
      "kind": "packaging"
    }
  ],
  "sections": [
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    "viewers",
    "readme",
    "breadcrumbs",
    "info"
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  "discovery_triggers": [
    "74ahct594pw"
  ],
  "discovery_pitch": "74AHCT594PW (Nexperia) component page with datasheet-verified CAD.",
  "author": {
    "name": "Ray",
    "email": "[email protected]"
  },
  "dependencies": {},
  "hero": {
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    "path": "docs/hero.png"
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    "74ahct594pw.glb",
    "74ahct594pw.step",
    "74ahct594pw.lbr",
    "docs/hero.png",
    "docs/74ahct594pw-datasheet.pdf",
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  "visibility": {
    "public": true
  },
  "updated_at": "2026-09-24T14:47:32.214Z"
}