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74AHCT594PW

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Nexperia Shift Registers, TSSOP-16. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.

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74AHCT594PW

Nexperia · Shift Registers · TSSOP-16

74AHCT594PW from Nexperia, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 Q1 output Parallel data output bit 1 from the 8-bit storage register. CMOS push-pull output; drive capability up to 8 mA at VCC = 4.5 V (VOL ≤ 0.44 V).
2 Q2 output Parallel data output bit 2 from the 8-bit storage register. CMOS push-pull output; drive capability up to 8 mA at VCC = 4.5 V.
3 Q3 output Parallel data output bit 3 from the 8-bit storage register. CMOS push-pull output; drive capability up to 8 mA at VCC = 4.5 V.
4 Q4 output Parallel data output bit 4 from the 8-bit storage register. CMOS push-pull output; drive capability up to 8 mA at VCC = 4.5 V.
5 Q5 output Parallel data output bit 5 from the 8-bit storage register. CMOS push-pull output; drive capability up to 8 mA at VCC = 4.5 V.
6 Q6 output Parallel data output bit 6 from the 8-bit storage register. CMOS push-pull output; drive capability up to 8 mA at VCC = 4.5 V.
7 Q7 output Parallel data output bit 7 (MSB) from the 8-bit storage register. CMOS push-pull output; drive capability up to 8 mA at VCC = 4.5 V.
8 GND power_in Ground reference (0 V). Maximum ground current 75 mA.
9 Q7S output Serial data output - the last stage of the shift register (before the storage latch). Used for cascading additional 74AHCT594 devices; changes on rising edge of SHCP.
10 SHR input Shift-register reset input, active LOW (asynchronous). Driving SHR LOW clears the internal 8-bit shift register only; the storage register is unaffected. Schmitt-trigger TTL-compatible input, overvoltage tolerant to 5.5 V.
11 SHCP input Shift-register clock input. Data on DS is shifted into the shift register on the LOW-to-HIGH transition. Schmitt-trigger TTL-compatible input; fmax ≥ 70 MHz at VCC = 4.5 V-5.5 V.
12 STCP input Storage-register clock input. On the LOW-to-HIGH transition, the contents of the shift register are latched into the 8-bit storage register and appear on Q0-Q7. Schmitt-trigger TTL-compatible input.
13 STR input Storage-register reset input, active LOW (asynchronous). Driving STR LOW forces all parallel outputs Q0-Q7 LOW; the shift register is unaffected. Schmitt-trigger TTL-compatible input, overvoltage tolerant to 5.5 V.
14 DS input Serial data input to the shift register. Sampled on the LOW-to-HIGH transition of SHCP. tsu = 3 ns, th = 2 ns (VCC = 4.5 V). Schmitt-trigger TTL-compatible input.
15 Q0 output Parallel data output bit 0 (LSB) from the 8-bit storage register. CMOS push-pull output; drive capability up to 8 mA at VCC = 4.5 V.
16 VCC power_in Positive supply voltage. Operating range 4.5 V to 5.5 V for the 74AHCT594 (TTL-level inputs). Absolute maximum 7.0 V.

Key specifications

Parameter Value
Manufacturer Nexperia
Package TSSOP-16
Category Logic
Pins 16

Ordering variants

Same part, different packaging or reel option.

  • 74AHCT594PW
  • 74AHCT594PWD
  • 74AHCT594PWBQ

CAD (KiCad official)

  • Symbol: 74AHCT594PW
  • Footprint: Package_SO:TSSOP-16_4.4x5mm_P0.65mm
  • 3D model: TSSOP-16 (KiCad packages3D, STEP)
  • 3D model files: 74ahct594pw-etched.step / 74ahct594pw-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); 74ahct594pw.step / 74ahct594pw.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Nexperia datasheet (19 pp, sha256 904f218d5c3a23ea, retrieved 2026-08-17, tier: manufacturer)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF