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74AHCT574PW

Public Made by Adom

by adom

Nexperia Flip Flops, TSSOP-20. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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74AHCT574PW

Nexperia · Flip Flops · TSSOP-20

74AHCT574PW from Nexperia, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 OE input Active-LOW 3-state output enable; a HIGH forces outputs Q0 to Q7 into the high-impedance OFF-state without changing the flip-flop contents.
2 D0 input Data input to flip-flop 0, captured on the LOW-to-HIGH CP transition; set-up time 3.0 ns and hold time 1.5 ns minimum at VCC 4.5 V to 5.5 V, and inputs are overvoltage tolerant to 5.5 V.
3 D1 input Data input to flip-flop 1, captured on the LOW-to-HIGH CP transition; set-up time 3.0 ns and hold time 1.5 ns minimum at VCC 4.5 V to 5.5 V, and inputs are overvoltage tolerant to 5.5 V.
4 D2 input Data input to flip-flop 2, captured on the LOW-to-HIGH CP transition; set-up time 3.0 ns and hold time 1.5 ns minimum at VCC 4.5 V to 5.5 V, and inputs are overvoltage tolerant to 5.5 V.
5 D3 input Data input to flip-flop 3, captured on the LOW-to-HIGH CP transition; set-up time 3.0 ns and hold time 1.5 ns minimum at VCC 4.5 V to 5.5 V, and inputs are overvoltage tolerant to 5.5 V.
6 D4 input Data input to flip-flop 4, captured on the LOW-to-HIGH CP transition; set-up time 3.0 ns and hold time 1.5 ns minimum at VCC 4.5 V to 5.5 V, and inputs are overvoltage tolerant to 5.5 V.
7 D5 input Data input to flip-flop 5, captured on the LOW-to-HIGH CP transition; set-up time 3.0 ns and hold time 1.5 ns minimum at VCC 4.5 V to 5.5 V, and inputs are overvoltage tolerant to 5.5 V.
8 D6 input Data input to flip-flop 6, captured on the LOW-to-HIGH CP transition; set-up time 3.0 ns and hold time 1.5 ns minimum at VCC 4.5 V to 5.5 V, and inputs are overvoltage tolerant to 5.5 V.
9 D7 input Data input to flip-flop 7, captured on the LOW-to-HIGH CP transition; set-up time 3.0 ns and hold time 1.5 ns minimum at VCC 4.5 V to 5.5 V, and inputs are overvoltage tolerant to 5.5 V.
10 GND power_in Ground (0 V) reference for all voltages on the device.
11 CP input Clock input; flip-flops load Dn on the LOW-to-HIGH transition, with a minimum CP pulse width of 5.5 ns at VCC 4.5 V to 5.5 V (CL 50 pF).
12 Q7 tri_state 3-state non-inverting flip-flop output 7, high-impedance when OE is HIGH.
13 Q6 tri_state 3-state non-inverting flip-flop output 6, high-impedance when OE is HIGH.
14 Q5 tri_state 3-state non-inverting flip-flop output 5, high-impedance when OE is HIGH.
15 Q4 tri_state 3-state non-inverting flip-flop output 4, high-impedance when OE is HIGH.
16 Q3 tri_state 3-state non-inverting flip-flop output 3, high-impedance when OE is HIGH.
17 Q2 tri_state 3-state non-inverting flip-flop output 2, high-impedance when OE is HIGH.
18 Q1 tri_state 3-state non-inverting flip-flop output 1, high-impedance when OE is HIGH.
19 Q0 tri_state 3-state non-inverting flip-flop output 0, high-impedance when OE is HIGH.
20 VCC power_in Supply voltage: 4.5 V to 5.5 V recommended for the 74AHCT574; absolute maximum 7.0 V.

Key specifications

Parameter Value
Manufacturer Nexperia
Package TSSOP-20
Category Logic
Pins 20

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
supply voltage VCC -0.5 7 V 4
input voltage VI -0.5 7 V 4
input clamping current IIK -20 mA VI < -0.5 V 4
output clamping current IOK -20 20 mA VO < -0.5 V or VO > VCC + 0.5 V 4
output current IO -25 25 mA VO = -0.5 V to (VCC + 0.5 V) 4
supply current ICC 75 mA 4
ground current IGND -75 mA 4
storage temperature Tstg -65 150 °C 4
total power dissipation Ptot 500 mW Tamb = -40 °C to +125 °C 4
supply voltage VCC 4.5 5 5.5 V 74AHCT574 4
input voltage VI 0 5.5 V 4
output voltage VO 0 V 4
ambient temperature Tamb -40 25 125 °C 4
input transition rise and fall rate Δt/ΔV 20 ns/V VCC = 5.0 V ± 0.5 V 4
HIGH-level input voltage VIH 2 V 25 °C; VCC = 4.5 V to 5.5 V 6
LOW-level input voltage VIL 0.8 V 25 °C; VCC = 4.5 V to 5.5 V 6
HIGH-level output voltage VOH 4.4 4.5 V 25 °C; VI = VIH or VIL; VCC = 4.5 V; IO = -50 μA 6
HIGH-level output voltage VOH 4.4 V -40 °C to +125 °C; VI = VIH or VIL; VCC = 4.5 V; IO = -50 μA 6
HIGH-level output voltage VOH 3.94 V 25 °C; VI = VIH or VIL; VCC = 4.5 V; IO = -8.0 mA 6
HIGH-level output voltage VOH 3.7 V -40 °C to +125 °C; VI = VIH or VIL; VCC = 4.5 V; IO = -8.0 mA 6
LOW-level output voltage VOL 0 0.1 V 25 °C; VI = VIH or VIL; VCC = 4.5 V; IO = 50 μA 6
LOW-level output voltage VOL 0.1 V -40 °C to +125 °C; VI = VIH or VIL; VCC = 4.5 V; IO = 50 μA 6
LOW-level output voltage VOL 0.36 V 25 °C; VI = VIH or VIL; VCC = 4.5 V; IO = 8.0 mA 6
LOW-level output voltage VOL 0.55 V -40 °C to +125 °C; VI = VIH or VIL; VCC = 4.5 V; IO = 8.0 mA 6
OFF-state output current IOZ -0.25 0.25 μA 25 °C; VI = VIH or VIL; VO = VCC or GND; VCC = 5.5 V 6
OFF-state output current IOZ -10 10 μA -40 °C to +125 °C; VI = VIH or VIL; VO = VCC or GND; VCC = 5.5 V 6
input leakage current II 0.1 μA 25 °C; VI = 5.5 V or GND; VCC = 0 V to 5.5 V 6
input leakage current II 2 μA -40 °C to +125 °C; VI = 5.5 V or GND; VCC = 0 V to 5.5 V 6
supply current ICC 4 μA 25 °C; VI = VCC or GND; IO = 0 A; VCC = 5.5 V 6
supply current ICC 80 μA -40 °C to +125 °C; VI = VCC or GND; IO = 0 A; VCC = 5.5 V 6
additional supply current ΔICC 1.35 mA 25 °C; per input pin; VI = VCC − 2.1 V; IO = 0 A; other pins at VCC or GND; VCC = 4.5 V to 5.5 V 6
additional supply current ΔICC 1.5 mA -40 °C to +125 °C; per input pin; VI = VCC − 2.1 V; IO = 0 A; other pins at VCC or GND; VCC = 4.5 V to 5.5 V 6
input capacitance CI 3 10 pF 25 °C 6
input capacitance CI 10 pF -40 °C to +125 °C 6
propagation delay CP to Qn tpd 4.4 8.6 ns 25 °C; CL = 15 pF; VCC = 4.5 V to 5.5 V 8
propagation delay CP to Qn tpd 1 11 ns -40 °C to +125 °C; CL = 15 pF; VCC = 4.5 V to 5.5 V 8
propagation delay CP to Qn tpd 6.3 10.6 ns 25 °C; CL = 50 pF; VCC = 4.5 V to 5.5 V 8
propagation delay CP to Qn tpd 1 13.5 ns -40 °C to +125 °C; CL = 50 pF; VCC = 4.5 V to 5.5 V 8
enable time OE to Qn ten 4.3 9 ns 25 °C; CL = 15 pF; VCC = 4.5 V to 5.5 V 8
enable time OE to Qn ten 1 11.5 ns -40 °C to +125 °C; CL = 15 pF; VCC = 4.5 V to 5.5 V 8
enable time OE to Qn ten 6.1 11 ns 25 °C; CL = 50 pF; VCC = 4.5 V to 5.5 V 8
enable time OE to Qn ten 1 14 ns -40 °C to +125 °C; CL = 50 pF; VCC = 4.5 V to 5.5 V 8
disable time OE to Qn tdis 4.3 9 ns 25 °C; CL = 15 pF; VCC = 4.5 V to 5.5 V 8
disable time OE to Qn tdis 1 11.5 ns -40 °C to +125 °C; CL = 15 pF; VCC = 4.5 V to 5.5 V 8
disable time OE to Qn tdis 6.2 10.1 ns 25 °C; CL = 50 pF; VCC = 4.5 V to 5.5 V 8
disable time OE to Qn tdis 1 13 ns -40 °C to +125 °C; CL = 50 pF; VCC = 4.5 V to 5.5 V 8
maximum frequency fmax 130 180 MHz 25 °C; CL = 15 pF; VCC = 4.5 V to 5.5 V; CP 8
maximum frequency fmax 110 MHz -40 °C to +125 °C; CL = 15 pF; VCC = 4.5 V to 5.5 V; CP 8
maximum frequency fmax 85 115 MHz 25 °C; CL = 50 pF; VCC = 4.5 V to 5.5 V; CP 8
maximum frequency fmax 75 MHz -40 °C to +125 °C; CL = 50 pF; VCC = 4.5 V to 5.5 V; CP 8
clock pulse width tW 5 ns 25 °C; CP HIGH or LOW; VCC = 4.5 V to 5.5 V; CL = 50 pF 8
clock pulse width tW 5.5 ns -40 °C to +125 °C; CP HIGH or LOW; VCC = 4.5 V to 5.5 V; CL = 50 pF 8
set-up time Dn to CP tsu 3 ns 25 °C; Dn to CP; VCC = 4.5 V to 5.5 V; CL = 50 pF 8
set-up time Dn to CP tsu 3.5 ns -40 °C to +125 °C; Dn to CP; VCC = 4.5 V to 5.5 V; CL = 50 pF 8
hold time Dn to CP th 1.5 ns 25 °C; Dn to CP; VCC = 4.5 V to 5.5 V; CL = 50 pF 8

CAD (KiCad official)

  • Symbol: 74AHCT574PW
  • Footprint: Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm
  • 3D model: TSSOP-20 (KiCad packages3D, STEP)
  • 3D model files: 74ahct574pw-etched.step / 74ahct574pw-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); 74ahct574pw.step / 74ahct574pw.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Nexperia datasheet (17 pp, sha256 d20240a58657e001, retrieved 2026-10-18, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF