component
74AHCT32PW-Q100J
Public Made by Adomby adom
Nexperia Logic Gates, TSSOP-14. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.
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page.json+166−8@@ -1,13 +1,176 @@ {+ "schema_version": 1,+ "type": "component", "slug": "74ahct32pw-q100j",+ "title": "74AHCT32PW-Q100J",+ "brief": "Nexperia Logic Gates, TSSOP-14. Datasheet-verified pinout, KiCad symbol/footprint/3D.", "version": "0.1.0",- "type": "component",- "description": "Nexperia Logic Gates, TSSOP-14. Datasheet-verified pinout, KiCad symbol/footprint/3D.",+ "license": "CC-BY-SA-4.0", "tags": [ "component", "logic", "74ahct32pw-q100j" ],+ "component": {+ "mpn": "74AHCT32PW-Q100J",+ "manufacturer": "Nexperia",+ "package": "TSSOP-14",+ "pin_count": 14,+ "category": "Logic",+ "subcategory": "Logic Gates",+ "datasheet": "https://assets.nexperia.com/documents/data-sheet/74AHCT32PW-Q100J.pdf",+ "parts": {+ "symbol": "74ahct32pw-q100j.kicad_sym",+ "footprint": "74ahct32pw-q100j.kicad_mod",+ "model_3d": "74ahct32pw-q100j.glb",+ "model_3d_step": "74ahct32pw-q100j.step",+ "lbr": "74ahct32pw-q100j.lbr"+ },+ "distributor_links": {},+ "pins": [+ {+ "number": "1",+ "name": "1A",+ "type": "input",+ "description": "Gate 1 data input A. TTL-level Schmitt-trigger input, overvoltage tolerant to 5.5 V independent of VCC. V_IH \u2265 2.0 V, V_IL \u2264 0.8 V (VCC = 4.5-5.5 V)."+ },+ {+ "number": "2",+ "name": "1B",+ "type": "input",+ "description": "Gate 1 data input B. TTL-level Schmitt-trigger input, overvoltage tolerant to 5.5 V. V_IH \u2265 2.0 V, V_IL \u2264 0.8 V (VCC = 4.5-5.5 V)."+ },+ {+ "number": "3",+ "name": "1Y",+ "type": "output",+ "description": "Gate 1 OR output (1Y = 1A OR 1B). Push-pull CMOS output; V_OH \u2265 3.94 V and V_OL \u2264 0.36 V at \u00b18 mA drive with VCC = 4.5 V. Clamping current limited to \u00b120 mA."+ },+ {+ "number": "4",+ "name": "2A",+ "type": "input",+ "description": "Gate 2 data input A. TTL-level Schmitt-trigger input, overvoltage tolerant to 5.5 V."+ },+ {+ "number": "5",+ "name": "2B",+ "type": "input",+ "description": "Gate 2 data input B. TTL-level Schmitt-trigger input, overvoltage tolerant to 5.5 V."+ },+ {+ "number": "6",+ "name": "2Y",+ "type": "output",+ "description": "Gate 2 OR output (2Y = 2A OR 2B). Push-pull CMOS output; \u00b18 mA drive at VCC = 4.5 V."+ },+ {+ "number": "7",+ "name": "GND",+ "type": "power_in",+ "description": "Ground (0 V) reference for the device. All input and output voltages are referenced to this pin."+ },+ {+ "number": "8",+ "name": "3Y",+ "type": "output",+ "description": "Gate 3 OR output (3Y = 3A OR 3B). Push-pull CMOS output; \u00b18 mA drive at VCC = 4.5 V."+ },+ {+ "number": "9",+ "name": "3A",+ "type": "input",+ "description": "Gate 3 data input A. TTL-level Schmitt-trigger input, overvoltage tolerant to 5.5 V."+ },+ {+ "number": "10",+ "name": "3B",+ "type": "input",+ "description": "Gate 3 data input B. TTL-level Schmitt-trigger input, overvoltage tolerant to 5.5 V."+ },+ {+ "number": "11",+ "name": "4Y",+ "type": "output",+ "description": "Gate 4 OR output (4Y = 4A OR 4B). Push-pull CMOS output; \u00b18 mA drive at VCC = 4.5 V."+ },+ {+ "number": "12",+ "name": "4A",+ "type": "input",+ "description": "Gate 4 data input A. TTL-level Schmitt-trigger input, overvoltage tolerant to 5.5 V."+ },+ {+ "number": "13",+ "name": "4B",+ "type": "input",+ "description": "Gate 4 data input B. TTL-level Schmitt-trigger input, overvoltage tolerant to 5.5 V."+ },+ {+ "number": "14",+ "name": "VCC",+ "type": "power_in",+ "description": "Positive supply voltage, 2.0 V to 5.5 V recommended (4.5 V to 5.5 V for guaranteed TTL-input timing). Absolute maximum 7.0 V. Bypass locally with a 100 nF ceramic capacitor."+ }+ ],+ "provenance": {+ "extractor": "ds2sf",+ "datasheet": {+ "url": "https://assets.nexperia.com/documents/data-sheet/74AHCT32PW-Q100J.pdf",+ "pages": 13,+ "sha256": "584eb7f5ed99cfbb",+ "source_tier": "mfr"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 14,+ "described": 14,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ }+ },+ "metadata": {+ "specs": {+ "Manufacturer": "Nexperia",+ "Package": "TSSOP-14",+ "Category": "Logic",+ "Pins": "14"+ }+ },+ "variants": [+ {+ "mpn": "74AHCT32PW-Q100J",+ "kind": "packaging"+ },+ {+ "mpn": "74AHCT32PW-Q100JD-Q100",+ "kind": "packaging"+ },+ {+ "mpn": "74AHCT32PW-Q100JBQ-Q100",+ "kind": "packaging"+ }+ ],+ "sections": [+ "hero",+ "viewers",+ "readme",+ "breadcrumbs",+ "info"+ ],+ "discovery_triggers": [+ "74ahct32pw-q100j"+ ],+ "discovery_pitch": "74AHCT32PW-Q100J (Nexperia) component page with datasheet-verified CAD.",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }, "dependencies": {}, "hero": { "type": "image",@@ -25,10 +188,5 @@ "docs/74ahct32pw-q100j-datasheet.pdf", "viewers/symbol.html", "viewers/footprint.html"- ],- "visibility": "public",- "author": {- "name": "Ray",- "email": "[email protected]"- }+ ] }