component
74AHCT273PW
Public Made by Adomby adom
Nexperia Flip Flops, TSSOP-20. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
Open in new tab ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.
Symbol & Footprint
Schematic Symbol
Open full view ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
PCB Footprint
Open full view ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
Datasheet
Open in new tab ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
README
markdown74AHCT273PW
Nexperia · Flip Flops · TSSOP-20
74AHCT273PW from Nexperia, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | MR | input | Master reset input (active LOW); a LOW forces all outputs Qn LOW independently of the clock and data inputs. |
| 2 | Q0 | output | Flip-flop output Q0, which takes the state of D0 on the LOW-to-HIGH transition of CP and is forced LOW by MR. |
| 3 | D0 | input | Data input D0, which must meet the set-up time (3.0 ns min) and hold time (1.0 ns min) relative to CP for 4.5 V to 5.5 V operation. |
| 4 | D1 | input | Data input D1, which must meet the set-up time (3.0 ns min) and hold time (1.0 ns min) relative to CP for 4.5 V to 5.5 V operation. |
| 5 | Q1 | output | Flip-flop output Q1, which takes the state of D1 on the LOW-to-HIGH transition of CP and is forced LOW by MR. |
| 6 | Q2 | output | Flip-flop output Q2, which takes the state of D2 on the LOW-to-HIGH transition of CP and is forced LOW by MR. |
| 7 | D2 | input | Data input D2, which must meet the set-up time (3.0 ns min) and hold time (1.0 ns min) relative to CP for 4.5 V to 5.5 V operation. |
| 8 | D3 | input | Data input D3, which must meet the set-up time (3.0 ns min) and hold time (1.0 ns min) relative to CP for 4.5 V to 5.5 V operation. |
| 9 | Q3 | output | Flip-flop output Q3, which takes the state of D3 on the LOW-to-HIGH transition of CP and is forced LOW by MR. |
| 10 | GND | power_in | Ground (0 V) reference for all voltages on the device. |
| 11 | CP | input | Clock input, LOW-to-HIGH edge-triggered; Dn values are loaded into the flip-flops on this transition. |
| 12 | Q4 | output | Flip-flop output Q4, which takes the state of D4 on the LOW-to-HIGH transition of CP and is forced LOW by MR. |
| 13 | D4 | input | Data input D4, which must meet the set-up time (3.0 ns min) and hold time (1.0 ns min) relative to CP for 4.5 V to 5.5 V operation. |
| 14 | D5 | input | Data input D5, which must meet the set-up time (3.0 ns min) and hold time (1.0 ns min) relative to CP for 4.5 V to 5.5 V operation. |
| 15 | Q5 | output | Flip-flop output Q5, which takes the state of D5 on the LOW-to-HIGH transition of CP and is forced LOW by MR. |
| 16 | Q6 | output | Flip-flop output Q6, which takes the state of D6 on the LOW-to-HIGH transition of CP and is forced LOW by MR. |
| 17 | D6 | input | Data input D6, which must meet the set-up time (3.0 ns min) and hold time (1.0 ns min) relative to CP for 4.5 V to 5.5 V operation. |
| 18 | D7 | input | Data input D7, which must meet the set-up time (3.0 ns min) and hold time (1.0 ns min) relative to CP for 4.5 V to 5.5 V operation. |
| 19 | Q7 | output | Flip-flop output Q7, which takes the state of D7 on the LOW-to-HIGH transition of CP and is forced LOW by MR. |
| 20 | VCC | power_in | Supply voltage; the 74AHCT273 is specified for 4.5 V to 5.5 V (recommended operating range). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Nexperia |
| Package | TSSOP-20 |
| Category | Logic |
| Pins | 20 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VCC supply voltage | VCC | -0.5 | 7 | V | 4 | ||
| Input voltage | VI | -0.5 | 7 | V | 4 | ||
| Input clamping current | IIK | -20 | mA | VI < -0.5 V | 4 | ||
| Output clamping current | IOK | -20 | 20 | mA | VO < -0.5 V or VO > VCC + 0.5 V | 4 | |
| Output current | IO | -25 | 25 | mA | VO = -0.5 V to (VCC + 0.5 V) | 4 | |
| Supply current | ICC | 75 | mA | 4 | |||
| Ground current | IGND | -75 | mA | 4 | |||
| Storage temperature | Tstg | -65 | 150 | °C | 4 | ||
| Total power dissipation | Ptot | 500 | mW | Tamb = -40 °C to +125 °C | 4 | ||
| Supply voltage (74AHCT273) | VCC | 4.5 | 5 | 5.5 | V | 5 | |
| Input voltage (74AHCT273) | VI | 0 | 5.5 | V | 5 | ||
| Output voltage (74AHCT273) | VO | 0 | V | maximum printed as VCC (symbolic, not numeric) | 5 | ||
| Ambient temperature (74AHCT273) | Tamb | -40 | 25 | 125 | °C | 5 | |
| Input transition rise and fall rate (74AHCT273) | Δt/ΔV | 20 | ns/V | VCC = 5.0 V ± 0.5 V | 5 | ||
| HIGH-level input voltage (74AHCT273) | VIH | 2 | V | VCC = 4.5 V to 5.5 V; Tamb = -40 °C to +125 °C | 6 | ||
| LOW-level input voltage (74AHCT273) | VIL | 0.8 | V | VCC = 4.5 V to 5.5 V; Tamb = -40 °C to +125 °C | 6 | ||
| HIGH-level output voltage (74AHCT273) | VOH | 4.4 | V | VI = VIH or VIL; VCC = 4.5 V; IO = -50 μA; Tamb = -40 °C to +125 °C | 6 | ||
| HIGH-level output voltage (74AHCT273) | VOH | 3.94 | V | VI = VIH or VIL; VCC = 4.5 V; IO = -8.0 mA; Tamb = 25 °C | 6 | ||
| HIGH-level output voltage (74AHCT273) | VOH | 3.7 | V | VI = VIH or VIL; VCC = 4.5 V; IO = -8.0 mA; Tamb = -40 °C to +125 °C | 6 | ||
| LOW-level output voltage (74AHCT273) | VOL | 0 | 0.1 | V | VI = VIH or VIL; VCC = 4.5 V; IO = 50 μA; Tamb = -40 °C to +125 °C | 6 | |
| LOW-level output voltage (74AHCT273) | VOL | 0.36 | V | VI = VIH or VIL; VCC = 4.5 V; IO = 8.0 mA; Tamb = 25 °C | 6 | ||
| LOW-level output voltage (74AHCT273) | VOL | 0.55 | V | VI = VIH or VIL; VCC = 4.5 V; IO = 8.0 mA; Tamb = -40 °C to +125 °C | 6 | ||
| Input leakage current (74AHCT273) | II | 0.1 | μA | VI = 5.5 V or GND; VCC = 0 V to 5.5 V; Tamb = 25 °C | 6 | ||
| Input leakage current (74AHCT273) | II | 2 | μA | VI = 5.5 V or GND; VCC = 0 V to 5.5 V; Tamb = -40 °C to +125 °C | 6 | ||
| Supply current (74AHCT273) | ICC | 4 | μA | VI = VCC or GND; IO = 0 A; VCC = 5.5 V; Tamb = 25 °C | 6 | ||
| Supply current (74AHCT273) | ICC | 80 | μA | VI = VCC or GND; IO = 0 A; VCC = 5.5 V; Tamb = -40 °C to +125 °C | 6 | ||
| Additional supply current per input pin (74AHCT273) | ΔICC | 1.35 | mA | per input pin; VI = VCC - 2.1 V; other pins at VCC or GND; IO = 0 A; VCC = 4.5 V to 5.5 V; Tamb = 25 °C | 6 | ||
| Additional supply current per input pin (74AHCT273) | ΔICC | 1.5 | mA | per input pin; VI = VCC - 2.1 V; other pins at VCC or GND; IO = 0 A; VCC = 4.5 V to 5.5 V; Tamb = -40 °C to +125 °C | 6 | ||
| Input capacitance (74AHCT273) | CI | 3 | 10 | pF | Tamb = 25 °C | 6 | |
| Input capacitance (74AHCT273) | CI | 10 | pF | Tamb = -40 °C to +125 °C | 6 | ||
| Propagation delay CP to Qn, CL = 15 pF (74AHCT273) | tpd | 4 | 7.5 | ns | CP to Qn; see Fig. 5; CL = 15 pF; VCC = 4.5 V to 5.5 V; Tamb = 25 °C | 8 | |
| Propagation delay CP to Qn, CL = 15 pF (74AHCT273) | tpd | 1 | 9.5 | ns | CP to Qn; see Fig. 5; CL = 15 pF; VCC = 4.5 V to 5.5 V; Tamb = -40 °C to +125 °C | 8 | |
| Propagation delay CP to Qn, CL = 50 pF (74AHCT273) | tpd | 5.8 | 9.2 | ns | CP to Qn; see Fig. 5; CL = 50 pF; VCC = 4.5 V to 5.5 V; Tamb = 25 °C | 8 | |
| Propagation delay CP to Qn, CL = 50 pF (74AHCT273) | tpd | 1 | 11.5 | ns | CP to Qn; see Fig. 5; CL = 50 pF; VCC = 4.5 V to 5.5 V; Tamb = -40 °C to +125 °C | 8 | |
| Propagation delay MR to Qn, CL = 15 pF (74AHCT273) | tpd | 3.9 | 10 | ns | MR to Qn; see Fig. 6; CL = 15 pF; VCC = 4.5 V to 5.5 V; Tamb = 25 °C | 8 | |
| Propagation delay MR to Qn, CL = 15 pF (74AHCT273) | tpd | 1 | 12.5 | ns | MR to Qn; see Fig. 6; CL = 15 pF; VCC = 4.5 V to 5.5 V; Tamb = -40 °C to +125 °C | 8 | |
| Propagation delay MR to Qn, CL = 50 pF (74AHCT273) | tpd | 5.6 | 11 | ns | MR to Qn; see Fig. 6; CL = 50 pF; VCC = 4.5 V to 5.5 V; Tamb = 25 °C | 8 | |
| Propagation delay MR to Qn, CL = 50 pF (74AHCT273) | tpd | 1 | 14 | ns | MR to Qn; see Fig. 6; CL = 50 pF; VCC = 4.5 V to 5.5 V; Tamb = -40 °C to +125 °C | 8 | |
| Maximum frequency, CL = 15 pF (74AHCT273) | fmax | 75 | 120 | MHz | see Fig. 5; CL = 15 pF; VCC = 4.5 V to 5.5 V; Tamb = 25 °C | 8 | |
| Maximum frequency, CL = 15 pF (74AHCT273) | fmax | 65 | MHz | see Fig. 5; CL = 15 pF; VCC = 4.5 V to 5.5 V; Tamb = -40 °C to +125 °C | 8 | ||
| Maximum frequency, CL = 50 pF (74AHCT273) | fmax | 50 | 75 | MHz | see Fig. 5; CL = 50 pF; VCC = 4.5 V to 5.5 V; Tamb = 25 °C | 8 | |
| Maximum frequency, CL = 50 pF (74AHCT273) | fmax | 45 | MHz | see Fig. 5; CL = 50 pF; VCC = 4.5 V to 5.5 V; Tamb = -40 °C to +125 °C | 8 | ||
| Clock pulse width HIGH or LOW (74AHCT273) | tW | 5 | ns | CP HIGH or LOW; see Fig. 5; VCC = 4.5 V to 5.5 V; Tamb = 25 °C | 8 | ||
| Clock pulse width HIGH or LOW (74AHCT273) | tW | 6.5 | ns | CP HIGH or LOW; see Fig. 5; VCC = 4.5 V to 5.5 V; Tamb = -40 °C to +125 °C | 8 | ||
| Master reset pulse width LOW (74AHCT273) | tW | 5 | ns | MR LOW; see Fig. 6; VCC = 4.5 V to 5.5 V; Tamb = 25 °C | 8 | ||
| Master reset pulse width LOW (74AHCT273) | tW | 6 | ns | MR LOW; see Fig. 6; VCC = 4.5 V to 5.5 V; Tamb = -40 °C to +125 °C | 8 | ||
| Set-up time Dn to CP (74AHCT273) | tsu | 3 | ns | Dn to CP; see Fig. 7; VCC = 4.5 V to 5.5 V; Tamb = -40 °C to +125 °C | 8 | ||
| Hold time Dn to CP (74AHCT273) | th | 1 | ns | Dn to CP; see Fig. 7; VCC = 4.5 V to 5.5 V; Tamb = -40 °C to +125 °C | 8 | ||
| Recovery time MR to CP (74AHCT273) | trec | 2.5 | ns | MR to CP; see Fig. 6; VCC = 4.5 V to 5.5 V; Tamb = -40 °C to +125 °C | 8 |
CAD (KiCad official)
- Symbol:
74AHCT273PW - Footprint:
Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm - 3D model: TSSOP-20 (KiCad packages3D, STEP)
- 3D model files:
74ahct273pw-etched.step/74ahct273pw-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);74ahct273pw.step/74ahct273pw.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Nexperia datasheet (16 pp, sha256
dfa9bcf88bfd3ff7, retrieved 2026-10-18, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).