component
74AHCT240PW-Q100J
Public Made by Adomby adom
Nexperia Buffers, Drivers, Receivers, Transceivers, TSSOP-20. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdown74AHCT240PW-Q100J
Nexperia · Buffers, Drivers, Receivers, Transceivers · TSSOP-20
74AHCT240PW-Q100J from Nexperia, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1OE | input | Output enable input for outputs 1Y0 to 1Y3, active LOW; a HIGH level forces those outputs to the high-impedance OFF-state. |
| 2 | 1A0 | input | Data input 1A0 of the first 4-bit buffer; inputs are over-voltage tolerant and accept voltages up to 5.5 V in the recommended operating range. |
| 3 | 2Y0 | output | Inverting 3-state data output 2Y0 of the second 4-bit buffer. |
| 4 | 1A1 | input | Data input 1A1 of the first 4-bit buffer; inputs are over-voltage tolerant and accept voltages up to 5.5 V in the recommended operating range. |
| 5 | 2Y1 | output | Inverting 3-state data output 2Y1 of the second 4-bit buffer. |
| 6 | 1A2 | input | Data input 1A2 of the first 4-bit buffer; inputs are over-voltage tolerant and accept voltages up to 5.5 V in the recommended operating range. |
| 7 | 2Y2 | output | Inverting 3-state data output 2Y2 of the second 4-bit buffer. |
| 8 | 1A3 | input | Data input 1A3 of the first 4-bit buffer; inputs are over-voltage tolerant and accept voltages up to 5.5 V in the recommended operating range. |
| 9 | 2Y3 | output | Inverting 3-state data output 2Y3 of the second 4-bit buffer. |
| 10 | GND | power_in | Ground (0 V) reference for all voltages on the device. |
| 11 | 2A3 | input | Data input 2A3 of the second 4-bit buffer; inputs are over-voltage tolerant and accept voltages up to 5.5 V in the recommended operating range. |
| 12 | 1Y3 | output | Inverting 3-state data output 1Y3 of the first 4-bit buffer. |
| 13 | 2A2 | input | Data input 2A2 of the second 4-bit buffer; inputs are over-voltage tolerant and accept voltages up to 5.5 V in the recommended operating range. |
| 14 | 1Y2 | output | Inverting 3-state data output 1Y2 of the first 4-bit buffer. |
| 15 | 2A1 | input | Data input 2A1 of the second 4-bit buffer; inputs are over-voltage tolerant and accept voltages up to 5.5 V in the recommended operating range. |
| 16 | 1Y1 | output | Inverting 3-state data output 1Y1 of the first 4-bit buffer. |
| 17 | 2A0 | input | Data input 2A0 of the second 4-bit buffer; inputs are over-voltage tolerant and accept voltages up to 5.5 V in the recommended operating range. |
| 18 | 1Y0 | output | Inverting 3-state data output 1Y0 of the first 4-bit buffer. |
| 19 | 2OE | input | Output enable input for outputs 2Y0 to 2Y3, active LOW; a HIGH level forces those outputs to the high-impedance OFF-state. |
| 20 | VCC | power_in | Supply voltage; recommended operating range is 4.5 V to 5.5 V with 5.0 V typical, and the absolute maximum is -0.5 V to +7.0 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Nexperia |
| Package | TSSOP-20 |
| Category | Logic |
| Pins | 20 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage | VCC | -0.5 | 7 | V | 4 | ||
| Input voltage | VI | -0.5 | 7 | V | 4 | ||
| Input clamping current | IIK | -20 | mA | VI < -0.5 V | 4 | ||
| Output clamping current | IOK | -20 | 20 | mA | VO < -0.5 V or VO > VCC + 0.5 V | 4 | |
| Output current | IO | -25 | 25 | mA | VO = -0.5 V to (VCC + 0.5 V) | 4 | |
| Supply current | ICC | 75 | mA | 4 | |||
| Ground current | IGND | -75 | mA | 4 | |||
| Storage temperature | Tstg | -65 | 150 | °C | 4 | ||
| Total power dissipation | Ptot | 500 | mW | Tamb = -40 °C to +125 °C | 4 | ||
| Supply voltage | VCC | 4.5 | 5 | 5.5 | V | 4 | |
| Input voltage | VI | 0 | 5.5 | V | 4 | ||
| Output voltage | VO | 0 | V | 4 | |||
| Ambient temperature | Tamb | -40 | 25 | 125 | °C | 4 | |
| Input transition rise and fall rate | Δt/ΔV | 20 | ns/V | VCC = 5 V ± 0.5 V | 4 | ||
| HIGH-level input voltage | VIH | 2 | V | VCC = 4.5 V to 5.5 V | 5 | ||
| LOW-level input voltage | VIL | 0.8 | V | VCC = 4.5 V to 5.5 V | 5 | ||
| HIGH-level output voltage | VOH | 4.4 | V | VI = VIH or VIL; VCC = 4.5 V; IO = -50 μA | 5 | ||
| HIGH-level output voltage | VOH | 3.7 | V | VI = VIH or VIL; VCC = 4.5 V; IO = -8.0 mA | 5 | ||
| LOW-level output voltage | VOL | 0.1 | V | VI = VIH or VIL; VCC = 4.5 V; IO = 50 μA | 5 | ||
| LOW-level output voltage | VOL | 0.55 | V | VI = VIH or VIL; VCC = 4.5 V; IO = 8.0 mA | 5 | ||
| Input leakage current | II | 2 | μA | VI = 5.5 V or GND; VCC = 0 V to 5.5 V | 5 | ||
| OFF-state output current | IOZ | -10 | 10 | μA | VI = VIH or VIL; VO = VCC or GND; VCC = 5.5 V | 5 | |
| Supply current | ICC | 80 | μA | VI = VCC or GND; IO = 0 A; VCC = 5.5 V | 5 | ||
| Additional supply current | ΔICC | 1.5 | mA | per input pin; VI = VCC - 2.1 V; other pins at VCC or GND; IO = 0 A; VCC = 4.5 V to 5.5 V | 5 | ||
| Input capacitance | CI | 10 | pF | VI = VCC or GND | 5 | ||
| Propagation delay nAn to nYn | tpd | 1 | 11.9 | ns | VCC = 4.5 V to 5.5 V; CL = 50 pF | 6 | |
| Propagation delay nAn to nYn | tpd | 1 | 8.5 | ns | VCC = 4.5 V to 5.5 V; CL = 15 pF | 6 | |
| Enable time nOE to nYn | ten | 1 | 14.4 | ns | VCC = 4.5 V to 5.5 V; CL = 50 pF | 6 | |
| Disable time nOE to nYn | tdis | 1 | 11.5 | ns | VCC = 4.5 V to 5.5 V; CL = 50 pF | 6 | |
| Disable time nOE to nYn | tdis | 1 | 8.3 | ns | VCC = 4.5 V to 5.5 V; CL = 15 pF | 6 |
CAD (KiCad official)
- Symbol:
74AHCT240PW-Q100J - Footprint:
Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm - 3D model: TSSOP-20 (KiCad packages3D, STEP)
- 3D model files:
74ahct240pw-q100j-etched.step/74ahct240pw-q100j-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);74ahct240pw-q100j.step/74ahct240pw-q100j.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Nexperia datasheet (14 pp, sha256
29abde2d448bf392, retrieved 2026-10-21, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).