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74AHCT1G02GW

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Nexperia Logic ICs, SOT-353. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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74AHCT1G02GW

Nexperia · Logic ICs · SOT-353

74AHCT1G02GW from Nexperia, in a SOT-353. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 B input Data input B of the 2-input NOR gate; inputs are overvoltage tolerant up to 5.5 V and the 74AHCT1G02 uses TTL input levels.
2 A input Data input A of the 2-input NOR gate; inputs are overvoltage tolerant up to 5.5 V and the 74AHCT1G02 uses TTL input levels.
3 GND power_in Ground (0 V) reference for all voltages on the device.
4 Y output Data output Y of the NOR function, with output current limited to ±25 mA per the limiting values.
5 VCC power_in Supply voltage, 4.5 V to 5.5 V for the 74AHCT1G02 under recommended operating conditions, with an absolute maximum of 7.0 V.

Key specifications

Parameter Value
Manufacturer Nexperia
Package SOT-353
Category Logic ICs
Pins 5

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VCC -0.5 7 V 3
Input voltage VI -0.5 7 V 3
Input clamping current IIK -20 mA VI < -0.5 V 3
Output clamping current IOK -20 20 mA VO < -0.5 V or VO > VCC + 0.5 V 3
Output current IO -25 25 mA -0.5 V < VO < VCC + 0.5 V 3
Supply current ICC 75 mA 3
Ground current IGND -75 mA 3
Storage temperature Tstg -65 150 °C 3
Total power dissipation Ptot 250 mW Tamb = -40 °C to +125 °C 3
Supply voltage (74AHCT) VCC 4.5 5 5.5 V 3
Input voltage VI 0 5.5 V 3
Output voltage VO 0 V 3
Ambient temperature Tamb -40 25 125 °C 3
Input transition rise and fall rate Δt/ΔV 20 ns/V VCC = 5.0 V ± 0.5 V 3
HIGH-level input voltage VIH 2 V 25 °C; VCC = 4.5 V to 5.5 V 4
LOW-level input voltage VIL 0.8 V 25 °C; VCC = 4.5 V to 5.5 V 4
HIGH-level output voltage VOH 4.4 4.5 V 25 °C; VI = VIH or VIL; VCC = 4.5 V; IO = -50 μA 4
HIGH-level output voltage VOH 4.4 V -40 °C to +125 °C; VI = VIH or VIL; VCC = 4.5 V; IO = -50 μA 4
HIGH-level output voltage VOH 3.94 V 25 °C; VI = VIH or VIL; VCC = 4.5 V; IO = -8.0 mA 4
HIGH-level output voltage VOH 3.7 V -40 °C to +125 °C; VI = VIH or VIL; VCC = 4.5 V; IO = -8.0 mA 4
LOW-level output voltage VOL 0 0.1 V 25 °C; VI = VIH or VIL; VCC = 4.5 V; IO = 50 μA 4
LOW-level output voltage VOL 0.1 V -40 °C to +125 °C; VI = VIH or VIL; VCC = 4.5 V; IO = 50 μA 4
LOW-level output voltage VOL 0.36 V 25 °C; VI = VIH or VIL; VCC = 4.5 V; IO = 8.0 mA 4
LOW-level output voltage VOL 0.55 V -40 °C to +125 °C; VI = VIH or VIL; VCC = 4.5 V; IO = 8.0 mA 4
Input leakage current II 0.1 μA 25 °C; VI = 5.5 V or GND; VCC = 0 V to 5.5 V 4
Input leakage current II 2 μA -40 °C to +125 °C; VI = 5.5 V or GND; VCC = 0 V to 5.5 V 4
Supply current ICC 1 μA 25 °C; VI = VCC or GND; IO = 0 A; VCC = 5.5 V 4
Supply current ICC 40 μA -40 °C to +125 °C; VI = VCC or GND; IO = 0 A; VCC = 5.5 V 4
Additional supply current ΔICC 1.35 mA 25 °C; per input pin; VI = 3.4 V; other inputs at VCC or GND; IO = 0 A; VCC = 5.5 V 5
Additional supply current ΔICC 1.5 mA -40 °C to +125 °C; per input pin; VI = 3.4 V; other inputs at VCC or GND; IO = 0 A; VCC = 5.5 V 5
Input capacitance CI 1.5 10 pF 25 °C 5
Input capacitance CI 10 pF -40 °C to +125 °C 5
Propagation delay A and B to Y tpd 3.5 5.5 ns 25 °C; VCC = 4.5 V to 5.5 V; CL = 15 pF 5
Propagation delay A and B to Y tpd 1 7 ns -40 °C to +125 °C; VCC = 4.5 V to 5.5 V; CL = 15 pF 5
Propagation delay A and B to Y tpd 4.9 7.5 ns 25 °C; VCC = 4.5 V to 5.5 V; CL = 50 pF 5
Propagation delay A and B to Y tpd 1 9.5 ns -40 °C to +125 °C; VCC = 4.5 V to 5.5 V; CL = 50 pF 5
Power dissipation capacitance CPD 19 pF CL = 50 pF; f = 1 MHz; VI = GND to VCC 5

CAD (KiCad official)

  • Symbol: 74AHCT1G02GW
  • Footprint: Package_TO_SOT_SMD:SOT-353_SC-70-5
  • 3D model: SOT-353 (KiCad packages3D, STEP)
  • 3D model files: 74ahct1g02gw-etched.step / 74ahct1g02gw-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); 74ahct1g02gw.step / 74ahct1g02gw.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Nexperia datasheet (11 pp, sha256 1b8adc489eaf14f8, retrieved 2026-10-21, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus off (skipped (clean text read)), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF