component
74AHCT14PW-Q100
Public Made by Adomby adom
Nexperia Inverters, TSSOP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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74AHCT14PW-Q100
Nexperia · Inverters · TSSOP-14
74AHCT14PW-Q100 from Nexperia, in a TSSOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1A | input | Data input of inverter 1; input voltage range is 0 V to 5.5 V and inputs are overvoltage tolerant to 5.5 V. |
| 2 | 1Y | output | Data output of inverter 1; output current is limited to ±25 mA per the absolute maximum ratings. |
| 3 | 2A | input | Data input of inverter 2; input voltage range is 0 V to 5.5 V and inputs are overvoltage tolerant to 5.5 V. |
| 4 | 2Y | output | Data output of inverter 2; output current is limited to ±25 mA per the absolute maximum ratings. |
| 5 | 3A | input | Data input of inverter 3; input voltage range is 0 V to 5.5 V and inputs are overvoltage tolerant to 5.5 V. |
| 6 | 3Y | output | Data output of inverter 3; output current is limited to ±25 mA per the absolute maximum ratings. |
| 7 | GND | power_in | Ground pin at 0 V, the reference for all voltages in the datasheet. |
| 8 | 4Y | output | Data output of inverter 4; output current is limited to ±25 mA per the absolute maximum ratings. |
| 9 | 4A | input | Data input of inverter 4; input voltage range is 0 V to 5.5 V and inputs are overvoltage tolerant to 5.5 V. |
| 10 | 5Y | output | Data output of inverter 5; output current is limited to ±25 mA per the absolute maximum ratings. |
| 11 | 5A | input | Data input of inverter 5; input voltage range is 0 V to 5.5 V and inputs are overvoltage tolerant to 5.5 V. |
| 12 | 6Y | output | Data output of inverter 6; output current is limited to ±25 mA per the absolute maximum ratings. |
| 13 | 6A | input | Data input of inverter 6; input voltage range is 0 V to 5.5 V and inputs are overvoltage tolerant to 5.5 V. |
| 14 | VCC | power_in | Supply voltage; 4.5 V to 5.5 V for the 74AHCT14-Q100 variant (2.0 V to 5.5 V for 74AHC14-Q100). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Nexperia |
| Package | TSSOP-14 |
| Category | Logic |
| Pins | 14 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage (recommended) | VCC | 4.5 | 5 | 5.5 | V | 74AHCT14-Q100 column | 4 |
| Input voltage (recommended) | VI | 0 | 5.5 | V | 74AHCT14-Q100 column | 4 | |
| Output voltage (recommended) | VO | 0 | V | 74AHCT14-Q100 column; maximum printed as VCC | 4 | ||
| Ambient temperature (recommended) | Tamb | -40 | 25 | 125 | °C | 74AHCT14-Q100 column | 4 |
| Supply voltage (absolute maximum) | VCC | -0.5 | 7 | V | Voltages referenced to GND | 3 | |
| Input voltage (absolute maximum) | VI | -0.5 | 7 | V | Voltages referenced to GND | 3 | |
| Input clamping current | IIK | -20 | mA | VI < -0.5 V | 3 | ||
| Output clamping current | IOK | -20 | 20 | mA | VO < -0.5 V or VO > VCC + 0.5 V | 3 | |
| Output current | IO | -25 | 25 | mA | VO = -0.5 V to (VCC + 0.5 V) | 3 | |
| Supply current | ICC | 75 | mA | 3 | |||
| Ground current | IGND | -75 | mA | 3 | |||
| Storage temperature | Tstg | -65 | 150 | °C | 3 | ||
| Total power dissipation | Ptot | 500 | mW | Tamb = -40 °C to +125 °C | 3 | ||
| HIGH-level output voltage | VOH | 4.4 | 4.5 | V | VI = VT+ or VT-; IO = -50 μA; VCC = 4.5 V; Tamb = 25 °C | 5 | |
| HIGH-level output voltage | VOH | 4.4 | V | VI = VT+ or VT-; IO = -50 μA; VCC = 4.5 V; Tamb = -40 °C to +125 °C | 5 | ||
| HIGH-level output voltage | VOH | 3.94 | V | IO = -8.0 mA; VCC = 4.5 V; Tamb = 25 °C | 5 | ||
| HIGH-level output voltage | VOH | 3.7 | V | IO = -8.0 mA; VCC = 4.5 V; Tamb = -40 °C to +125 °C | 5 | ||
| LOW-level output voltage | VOL | 0 | 0.1 | V | VI = VT+ or VT-; IO = 50 μA; VCC = 4.5 V; Tamb = 25 °C | 5 | |
| LOW-level output voltage | VOL | 0.1 | V | VI = VT+ or VT-; IO = 50 μA; VCC = 4.5 V; Tamb = -40 °C to +125 °C | 5 | ||
| LOW-level output voltage | VOL | 0.36 | V | IO = 8.0 mA; VCC = 4.5 V; Tamb = 25 °C | 5 | ||
| LOW-level output voltage | VOL | 0.55 | V | IO = 8.0 mA; VCC = 4.5 V; Tamb = -40 °C to +125 °C | 5 | ||
| Input leakage current | II | 0.1 | μA | VI = 5.5 V or GND; VCC = 0 V to 5.5 V; Tamb = 25 °C | 5 | ||
| Input leakage current | II | 2 | μA | VI = 5.5 V or GND; VCC = 0 V to 5.5 V; Tamb = -40 °C to +125 °C | 5 | ||
| Supply current | ICC | 2 | μA | VI = VCC or GND; IO = 0 A; VCC = 5.5 V; Tamb = 25 °C | 5 | ||
| Supply current | ICC | 40 | μA | VI = VCC or GND; IO = 0 A; VCC = 5.5 V; Tamb = -40 °C to +125 °C | 5 | ||
| Additional supply current per input pin | ΔICC | 1.35 | mA | per input pin; VI = VCC - 2.1 V; other pins at VCC or GND; IO = 0 A; VCC = 4.5 V to 5.5 V; Tamb = 25 °C | 5 | ||
| Additional supply current per input pin | ΔICC | 1.5 | mA | per input pin; VI = VCC - 2.1 V; other pins at VCC or GND; IO = 0 A; VCC = 4.5 V to 5.5 V; Tamb = -40 °C to +125 °C | 5 | ||
| Input capacitance | CI | 3 | 10 | pF | 5 | ||
| Propagation delay nA to nY | tpd | 4 | 7 | ns | VCC = 4.5 V to 5.5 V; CL = 15 pF; see Fig. 4; Tamb = 25 °C | 6 | |
| Propagation delay nA to nY | tpd | 1 | 9 | ns | VCC = 4.5 V to 5.5 V; CL = 15 pF; see Fig. 4; Tamb = -40 °C to +125 °C | 6 | |
| Propagation delay nA to nY | tpd | 5.4 | 8 | ns | VCC = 4.5 V to 5.5 V; CL = 50 pF; see Fig. 4; Tamb = 25 °C | 6 | |
| Propagation delay nA to nY | tpd | 1 | 10 | ns | VCC = 4.5 V to 5.5 V; CL = 50 pF; see Fig. 4; Tamb = -40 °C to +125 °C | 6 | |
| Positive-going threshold voltage | VT+ | 1.9 | V | VCC = 4.5 V; Tamb = -40 °C to +125 °C | 8 | ||
| Positive-going threshold voltage | VT+ | 2.1 | V | VCC = 5.5 V; Tamb = -40 °C to +125 °C | 8 | ||
| Negative-going threshold voltage | VT- | 0.5 | V | VCC = 4.5 V; Tamb = -40 °C to +125 °C | 8 | ||
| Negative-going threshold voltage | VT- | 0.6 | V | VCC = 5.5 V; Tamb = -40 °C to +125 °C | 8 | ||
| Hysteresis voltage | VH | 0.4 | 1.4 | V | VCC = 4.5 V; Tamb = 25 °C | 8 | |
| Hysteresis voltage | VH | 0.35 | 1.4 | V | VCC = 4.5 V; Tamb = -40 °C to +125 °C | 8 | |
| Hysteresis voltage | VH | 0.4 | 1.5 | V | VCC = 5.5 V; Tamb = 25 °C | 8 | |
| Hysteresis voltage | VH | 0.35 | 1.5 | V | VCC = 5.5 V; Tamb = -40 °C to +125 °C | 8 |
CAD (KiCad official)
- Symbol:
74AHCT14PW-Q100 - Footprint:
Package_SO:TSSOP-14_4.4x5mm_P0.65mm - 3D model: TSSOP-14 (KiCad packages3D, STEP)
- 3D model files:
74ahct14pw-q100-etched.step/74ahct14pw-q100-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);74ahct14pw-q100.step/74ahct14pw-q100.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Nexperia datasheet (16 pp, sha256
f54912c285116747, retrieved 2026-10-19, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# 74AHCT14PW-Q100
**Nexperia** · Inverters · TSSOP-14
74AHCT14PW-Q100 from Nexperia, in a TSSOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1A | input | Data input of inverter 1; input voltage range is 0 V to 5.5 V and inputs are overvoltage tolerant to 5.5 V. |
| 2 | 1Y | output | Data output of inverter 1; output current is limited to ±25 mA per the absolute maximum ratings. |
| 3 | 2A | input | Data input of inverter 2; input voltage range is 0 V to 5.5 V and inputs are overvoltage tolerant to 5.5 V. |
| 4 | 2Y | output | Data output of inverter 2; output current is limited to ±25 mA per the absolute maximum ratings. |
| 5 | 3A | input | Data input of inverter 3; input voltage range is 0 V to 5.5 V and inputs are overvoltage tolerant to 5.5 V. |
| 6 | 3Y | output | Data output of inverter 3; output current is limited to ±25 mA per the absolute maximum ratings. |
| 7 | GND | power_in | Ground pin at 0 V, the reference for all voltages in the datasheet. |
| 8 | 4Y | output | Data output of inverter 4; output current is limited to ±25 mA per the absolute maximum ratings. |
| 9 | 4A | input | Data input of inverter 4; input voltage range is 0 V to 5.5 V and inputs are overvoltage tolerant to 5.5 V. |
| 10 | 5Y | output | Data output of inverter 5; output current is limited to ±25 mA per the absolute maximum ratings. |
| 11 | 5A | input | Data input of inverter 5; input voltage range is 0 V to 5.5 V and inputs are overvoltage tolerant to 5.5 V. |
| 12 | 6Y | output | Data output of inverter 6; output current is limited to ±25 mA per the absolute maximum ratings. |
| 13 | 6A | input | Data input of inverter 6; input voltage range is 0 V to 5.5 V and inputs are overvoltage tolerant to 5.5 V. |
| 14 | VCC | power_in | Supply voltage; 4.5 V to 5.5 V for the 74AHCT14-Q100 variant (2.0 V to 5.5 V for 74AHC14-Q100). |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Nexperia |
| Package | TSSOP-14 |
| Category | Logic |
| Pins | 14 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage (recommended) | VCC | 4.5 | 5 | 5.5 | V | 74AHCT14-Q100 column | 4 |
| Input voltage (recommended) | VI | 0 | | 5.5 | V | 74AHCT14-Q100 column | 4 |
| Output voltage (recommended) | VO | 0 | | | V | 74AHCT14-Q100 column; maximum printed as VCC | 4 |
| Ambient temperature (recommended) | Tamb | -40 | 25 | 125 | °C | 74AHCT14-Q100 column | 4 |
| Supply voltage (absolute maximum) | VCC | -0.5 | | 7 | V | Voltages referenced to GND | 3 |
| Input voltage (absolute maximum) | VI | -0.5 | | 7 | V | Voltages referenced to GND | 3 |
| Input clamping current | IIK | -20 | | | mA | VI < -0.5 V | 3 |
| Output clamping current | IOK | -20 | | 20 | mA | VO < -0.5 V or VO > VCC + 0.5 V | 3 |
| Output current | IO | -25 | | 25 | mA | VO = -0.5 V to (VCC + 0.5 V) | 3 |
| Supply current | ICC | | | 75 | mA | | 3 |
| Ground current | IGND | -75 | | | mA | | 3 |
| Storage temperature | Tstg | -65 | | 150 | °C | | 3 |
| Total power dissipation | Ptot | | | 500 | mW | Tamb = -40 °C to +125 °C | 3 |
| HIGH-level output voltage | VOH | 4.4 | 4.5 | | V | VI = VT+ or VT-; IO = -50 μA; VCC = 4.5 V; Tamb = 25 °C | 5 |
| HIGH-level output voltage | VOH | 4.4 | | | V | VI = VT+ or VT-; IO = -50 μA; VCC = 4.5 V; Tamb = -40 °C to +125 °C | 5 |
| HIGH-level output voltage | VOH | 3.94 | | | V | IO = -8.0 mA; VCC = 4.5 V; Tamb = 25 °C | 5 |
| HIGH-level output voltage | VOH | 3.7 | | | V | IO = -8.0 mA; VCC = 4.5 V; Tamb = -40 °C to +125 °C | 5 |
| LOW-level output voltage | VOL | | 0 | 0.1 | V | VI = VT+ or VT-; IO = 50 μA; VCC = 4.5 V; Tamb = 25 °C | 5 |
| LOW-level output voltage | VOL | | | 0.1 | V | VI = VT+ or VT-; IO = 50 μA; VCC = 4.5 V; Tamb = -40 °C to +125 °C | 5 |
| LOW-level output voltage | VOL | | | 0.36 | V | IO = 8.0 mA; VCC = 4.5 V; Tamb = 25 °C | 5 |
| LOW-level output voltage | VOL | | | 0.55 | V | IO = 8.0 mA; VCC = 4.5 V; Tamb = -40 °C to +125 °C | 5 |
| Input leakage current | II | | | 0.1 | μA | VI = 5.5 V or GND; VCC = 0 V to 5.5 V; Tamb = 25 °C | 5 |
| Input leakage current | II | | | 2 | μA | VI = 5.5 V or GND; VCC = 0 V to 5.5 V; Tamb = -40 °C to +125 °C | 5 |
| Supply current | ICC | | | 2 | μA | VI = VCC or GND; IO = 0 A; VCC = 5.5 V; Tamb = 25 °C | 5 |
| Supply current | ICC | | | 40 | μA | VI = VCC or GND; IO = 0 A; VCC = 5.5 V; Tamb = -40 °C to +125 °C | 5 |
| Additional supply current per input pin | ΔICC | | | 1.35 | mA | per input pin; VI = VCC - 2.1 V; other pins at VCC or GND; IO = 0 A; VCC = 4.5 V to 5.5 V; Tamb = 25 °C | 5 |
| Additional supply current per input pin | ΔICC | | | 1.5 | mA | per input pin; VI = VCC - 2.1 V; other pins at VCC or GND; IO = 0 A; VCC = 4.5 V to 5.5 V; Tamb = -40 °C to +125 °C | 5 |
| Input capacitance | CI | | 3 | 10 | pF | | 5 |
| Propagation delay nA to nY | tpd | | 4 | 7 | ns | VCC = 4.5 V to 5.5 V; CL = 15 pF; see Fig. 4; Tamb = 25 °C | 6 |
| Propagation delay nA to nY | tpd | 1 | | 9 | ns | VCC = 4.5 V to 5.5 V; CL = 15 pF; see Fig. 4; Tamb = -40 °C to +125 °C | 6 |
| Propagation delay nA to nY | tpd | | 5.4 | 8 | ns | VCC = 4.5 V to 5.5 V; CL = 50 pF; see Fig. 4; Tamb = 25 °C | 6 |
| Propagation delay nA to nY | tpd | 1 | | 10 | ns | VCC = 4.5 V to 5.5 V; CL = 50 pF; see Fig. 4; Tamb = -40 °C to +125 °C | 6 |
| Positive-going threshold voltage | VT+ | | | 1.9 | V | VCC = 4.5 V; Tamb = -40 °C to +125 °C | 8 |
| Positive-going threshold voltage | VT+ | | | 2.1 | V | VCC = 5.5 V; Tamb = -40 °C to +125 °C | 8 |
| Negative-going threshold voltage | VT- | 0.5 | | | V | VCC = 4.5 V; Tamb = -40 °C to +125 °C | 8 |
| Negative-going threshold voltage | VT- | 0.6 | | | V | VCC = 5.5 V; Tamb = -40 °C to +125 °C | 8 |
| Hysteresis voltage | VH | 0.4 | | 1.4 | V | VCC = 4.5 V; Tamb = 25 °C | 8 |
| Hysteresis voltage | VH | 0.35 | | 1.4 | V | VCC = 4.5 V; Tamb = -40 °C to +125 °C | 8 |
| Hysteresis voltage | VH | 0.4 | | 1.5 | V | VCC = 5.5 V; Tamb = 25 °C | 8 |
| Hysteresis voltage | VH | 0.35 | | 1.5 | V | VCC = 5.5 V; Tamb = -40 °C to +125 °C | 8 |
## CAD (KiCad official)
- Symbol: `74AHCT14PW-Q100`
- Footprint: `Package_SO:TSSOP-14_4.4x5mm_P0.65mm`
- 3D model: TSSOP-14 (KiCad packages3D, STEP)
- 3D model files: `74ahct14pw-q100-etched.step` / `74ahct14pw-q100-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `74ahct14pw-q100.step` / `74ahct14pw-q100.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Nexperia datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588908331495010304) (16 pp, sha256 `f54912c285116747`, retrieved 2026-10-19, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/74ahct14pw-q100-datasheet.pdf)