component
74AHCT138PW
Public Made by Adomby adom
Nexperia Logic ICs, TSSOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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74AHCT138PW
Nexperia · Logic ICs · TSSOP-16
74AHCT138PW from Nexperia, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | A0 | input | Address input A0 (binary weight 1) selects which output goes LOW when the device is enabled; inputs accept voltages up to 5.5 V and higher than VCC. |
| 2 | A1 | input | Address input A1 selects which output goes LOW when the device is enabled; inputs accept voltages up to 5.5 V and higher than VCC. |
| 3 | A2 | input | Address input A2 (binary weight 4) selects which output goes LOW when the device is enabled; inputs accept voltages up to 5.5 V and higher than VCC. |
| 4 | E1 | input | Active-LOW enable input; outputs are only decoded when E1 and E2 are LOW and E3 is HIGH, and unused enables must be tied to their active state. |
| 5 | E2 | input | Active-LOW enable input; outputs are only decoded when E1 and E2 are LOW and E3 is HIGH, and unused enables must be tied to their active state. |
| 6 | E3 | input | Active-HIGH enable input; must be HIGH (with E1 and E2 LOW) for the decoder outputs to be active, and unused enables must be tied to their active state. |
| 7 | Y7 | output | Decoder output 7, mutually exclusive and LOW when selected; every output is HIGH when the device is not enabled. |
| 8 | GND | power_in | Ground (0 V) reference for all voltages on the device. |
| 9 | Y6 | output | Decoder output 6, mutually exclusive and LOW when selected; every output is HIGH when the device is not enabled. |
| 10 | Y5 | output | Decoder output 5, mutually exclusive and LOW when selected; every output is HIGH when the device is not enabled. |
| 11 | Y4 | output | Decoder output 4, mutually exclusive and LOW when selected; every output is HIGH when the device is not enabled. |
| 12 | Y3 | output | Decoder output 3, mutually exclusive and LOW when selected; every output is HIGH when the device is not enabled. |
| 13 | Y2 | output | Decoder output 2, mutually exclusive and LOW when selected; every output is HIGH when the device is not enabled. |
| 14 | Y1 | output | Decoder output 1, mutually exclusive and LOW when selected; every output is HIGH when the device is not enabled. |
| 15 | Y0 | output | Decoder output 0, mutually exclusive and LOW when selected; every output is HIGH when the device is not enabled. |
| 16 | VCC | power_in | Supply voltage; recommended range is 2.0 V to 5.5 V for the 74AHC138 and 4.5 V to 5.5 V for the 74AHCT138. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Nexperia |
| Package | TSSOP-16 |
| Category | Logic ICs |
| Pins | 16 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VCC supply voltage | VCC | -0.5 | 7 | V | 4 | ||
| VI input voltage | VI | -0.5 | 7 | V | 4 | ||
| IIK input clamping current | IIK | -20 | mA | VI < 0.5 V [1] | 4 | ||
| IOK output clamping current | IOK | -20 | mA | VO < 0.5 V or VO > VCC + 0.5 V [1] | 4 | ||
| IO output current | IO | -25 | mA | VO = 0.5 V to (VCC + 0.5 V) | 4 | ||
| ICC supply current | ICC | 75 | mA | 4 | |||
| IGND ground current | IGND | -75 | mA | 4 | |||
| Tstg storage temperature | Tstg | -65 | 150 | C | 4 | ||
| Ptot total power dissipation, TSSOP16 package | Ptot | 500 | mW | Tamb = -40 C to +125 C | 4 | ||
| VCC supply voltage | VCC | 4.5 | 5 | 5.5 | V | 74AHCT138 column | 5 |
| VI input voltage | VI | 0 | 5.5 | V | 74AHCT138 column | 5 | |
| VO output voltage | VO | 0 | V | 74AHCT138 column; printed maximum is VCC (not numeric) | 5 | ||
| Tamb ambient temperature | Tamb | -40 | 25 | 125 | C | 74AHCT138 column | 5 |
| input transition rise and fall rate | t/V | 20 | ns/V | VCC = 5.0 V ± 0.5 V | 5 | ||
| HIGH-level input voltage | VIH | 2 | V | VCC = 4.5 V to 5.5 V; Tamb -40 C to +125 C | 6 | ||
| LOW-level input voltage | VIL | 0.8 | V | VCC = 4.5 V to 5.5 V; Tamb -40 C to +125 C | 6 | ||
| HIGH-level output voltage | VOH | 4.4 | 4.5 | V | VI = VIH or VIL; VCC = 4.5 V; IO = 50 µA; Tamb -40 C to +125 C | 6 | |
| HIGH-level output voltage | VOH | 3.7 | V | VI = VIH or VIL; VCC = 4.5 V; IO = 8.0 mA; Tamb -40 C to +125 C | 6 | ||
| LOW-level output voltage | VOL | 0 | 0.1 | V | VI = VIH or VIL; VCC = 4.5 V; IO = 50 µA; Tamb -40 C to +125 C | 6 | |
| LOW-level output voltage | VOL | 0.55 | V | VI = VIH or VIL; VCC = 4.5 V; IO = 8.0 mA; Tamb -40 C to +125 C | 6 | ||
| input leakage current | II | 2 | µA | VI = 5.5 V or GND; VCC = 0 V or 5.5 V; Tamb -40 C to +125 C | 6 | ||
| supply current | ICC | 80 | µA | VI = VCC or GND; IO = 0 A; VCC = 5.5 V; Tamb -40 C to +125 C | 6 | ||
| additional supply current | ICC | 1.5 | mA | per input pin; VI = VCC - 2.1 V; IO = 0 A; other pins at VCC or GND; VCC = 4.5 V to 5.5 V; Tamb -40 C to +125 C | 6 | ||
| input capacitance | CI | 3 | 10 | pF | 6 | ||
| propagation delay An to Yn | tpd | 1 | 4.4 | 13 | ns | An to Yn; see Figure 6; VCC = 4.5 V to 5.5 V; CL = 15 pF; Tamb -40 C to +125 C | 8 |
| propagation delay An to Yn | tpd | 1 | 6.2 | 14.5 | ns | An to Yn; see Figure 6; VCC = 4.5 V to 5.5 V; CL = 50 pF; Tamb -40 C to +125 C | 8 |
| propagation delay E3 to Yn | tpd | 1 | 4.3 | 11.5 | ns | E3 to Yn; see Figure 6; VCC = 4.5 V to 5.5 V; CL = 15 pF; Tamb -40 C to +125 C | 8 |
| propagation delay E3 to Yn | tpd | 1 | 6.2 | 13 | ns | E3 to Yn; see Figure 6; VCC = 4.5 V to 5.5 V; CL = 50 pF; Tamb -40 C to +125 C | 8 |
| propagation delay E1, E2 to Yn | tpd | 1 | 4.3 | 12 | ns | E1, E2 to Yn; see Figure 7; VCC = 4.5 V to 5.5 V; CL = 15 pF; Tamb -40 C to +125 C | 8 |
| propagation delay E1, E2 to Yn | tpd | 1 | 6.2 | 13.5 | ns | E1, E2 to Yn; see Figure 7; VCC = 4.5 V to 5.5 V; CL = 50 pF; Tamb -40 C to +125 C | 8 |
CAD (KiCad official)
- Symbol:
74AHCT138PW - Footprint:
Package_SO:TSSOP-16_4.4x5mm_P0.65mm - 3D model: TSSOP-16 (KiCad packages3D, STEP)
- 3D model files:
74ahct138pw-etched.step/74ahct138pw-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);74ahct138pw.step/74ahct138pw.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Nexperia datasheet (17 pp, sha256
63520b5b696b050e, retrieved 2026-10-18, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# 74AHCT138PW
**Nexperia** · Logic ICs · TSSOP-16
74AHCT138PW from Nexperia, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | A0 | input | Address input A0 (binary weight 1) selects which output goes LOW when the device is enabled; inputs accept voltages up to 5.5 V and higher than VCC. |
| 2 | A1 | input | Address input A1 selects which output goes LOW when the device is enabled; inputs accept voltages up to 5.5 V and higher than VCC. |
| 3 | A2 | input | Address input A2 (binary weight 4) selects which output goes LOW when the device is enabled; inputs accept voltages up to 5.5 V and higher than VCC. |
| 4 | E1 | input | Active-LOW enable input; outputs are only decoded when E1 and E2 are LOW and E3 is HIGH, and unused enables must be tied to their active state. |
| 5 | E2 | input | Active-LOW enable input; outputs are only decoded when E1 and E2 are LOW and E3 is HIGH, and unused enables must be tied to their active state. |
| 6 | E3 | input | Active-HIGH enable input; must be HIGH (with E1 and E2 LOW) for the decoder outputs to be active, and unused enables must be tied to their active state. |
| 7 | Y7 | output | Decoder output 7, mutually exclusive and LOW when selected; every output is HIGH when the device is not enabled. |
| 8 | GND | power_in | Ground (0 V) reference for all voltages on the device. |
| 9 | Y6 | output | Decoder output 6, mutually exclusive and LOW when selected; every output is HIGH when the device is not enabled. |
| 10 | Y5 | output | Decoder output 5, mutually exclusive and LOW when selected; every output is HIGH when the device is not enabled. |
| 11 | Y4 | output | Decoder output 4, mutually exclusive and LOW when selected; every output is HIGH when the device is not enabled. |
| 12 | Y3 | output | Decoder output 3, mutually exclusive and LOW when selected; every output is HIGH when the device is not enabled. |
| 13 | Y2 | output | Decoder output 2, mutually exclusive and LOW when selected; every output is HIGH when the device is not enabled. |
| 14 | Y1 | output | Decoder output 1, mutually exclusive and LOW when selected; every output is HIGH when the device is not enabled. |
| 15 | Y0 | output | Decoder output 0, mutually exclusive and LOW when selected; every output is HIGH when the device is not enabled. |
| 16 | VCC | power_in | Supply voltage; recommended range is 2.0 V to 5.5 V for the 74AHC138 and 4.5 V to 5.5 V for the 74AHCT138. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Nexperia |
| Package | TSSOP-16 |
| Category | Logic ICs |
| Pins | 16 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VCC supply voltage | VCC | -0.5 | | 7 | V | | 4 |
| VI input voltage | VI | -0.5 | | 7 | V | | 4 |
| IIK input clamping current | IIK | -20 | | | mA | VI < 0.5 V [1] | 4 |
| IOK output clamping current | IOK | | | -20 | mA | VO < 0.5 V or VO > VCC + 0.5 V [1] | 4 |
| IO output current | IO | | | -25 | mA | VO = 0.5 V to (VCC + 0.5 V) | 4 |
| ICC supply current | ICC | | | 75 | mA | | 4 |
| IGND ground current | IGND | -75 | | | mA | | 4 |
| Tstg storage temperature | Tstg | -65 | | 150 | C | | 4 |
| Ptot total power dissipation, TSSOP16 package | Ptot | | | 500 | mW | Tamb = -40 C to +125 C | 4 |
| VCC supply voltage | VCC | 4.5 | 5 | 5.5 | V | 74AHCT138 column | 5 |
| VI input voltage | VI | 0 | | 5.5 | V | 74AHCT138 column | 5 |
| VO output voltage | VO | 0 | | | V | 74AHCT138 column; printed maximum is VCC (not numeric) | 5 |
| Tamb ambient temperature | Tamb | -40 | 25 | 125 | C | 74AHCT138 column | 5 |
| input transition rise and fall rate | t/V | | | 20 | ns/V | VCC = 5.0 V ± 0.5 V | 5 |
| HIGH-level input voltage | VIH | 2 | | | V | VCC = 4.5 V to 5.5 V; Tamb -40 C to +125 C | 6 |
| LOW-level input voltage | VIL | | | 0.8 | V | VCC = 4.5 V to 5.5 V; Tamb -40 C to +125 C | 6 |
| HIGH-level output voltage | VOH | 4.4 | 4.5 | | V | VI = VIH or VIL; VCC = 4.5 V; IO = 50 µA; Tamb -40 C to +125 C | 6 |
| HIGH-level output voltage | VOH | 3.7 | | | V | VI = VIH or VIL; VCC = 4.5 V; IO = 8.0 mA; Tamb -40 C to +125 C | 6 |
| LOW-level output voltage | VOL | | 0 | 0.1 | V | VI = VIH or VIL; VCC = 4.5 V; IO = 50 µA; Tamb -40 C to +125 C | 6 |
| LOW-level output voltage | VOL | | | 0.55 | V | VI = VIH or VIL; VCC = 4.5 V; IO = 8.0 mA; Tamb -40 C to +125 C | 6 |
| input leakage current | II | | | 2 | µA | VI = 5.5 V or GND; VCC = 0 V or 5.5 V; Tamb -40 C to +125 C | 6 |
| supply current | ICC | | | 80 | µA | VI = VCC or GND; IO = 0 A; VCC = 5.5 V; Tamb -40 C to +125 C | 6 |
| additional supply current | ICC | | | 1.5 | mA | per input pin; VI = VCC - 2.1 V; IO = 0 A; other pins at VCC or GND; VCC = 4.5 V to 5.5 V; Tamb -40 C to +125 C | 6 |
| input capacitance | CI | | 3 | 10 | pF | | 6 |
| propagation delay An to Yn | tpd | 1 | 4.4 | 13 | ns | An to Yn; see Figure 6; VCC = 4.5 V to 5.5 V; CL = 15 pF; Tamb -40 C to +125 C | 8 |
| propagation delay An to Yn | tpd | 1 | 6.2 | 14.5 | ns | An to Yn; see Figure 6; VCC = 4.5 V to 5.5 V; CL = 50 pF; Tamb -40 C to +125 C | 8 |
| propagation delay E3 to Yn | tpd | 1 | 4.3 | 11.5 | ns | E3 to Yn; see Figure 6; VCC = 4.5 V to 5.5 V; CL = 15 pF; Tamb -40 C to +125 C | 8 |
| propagation delay E3 to Yn | tpd | 1 | 6.2 | 13 | ns | E3 to Yn; see Figure 6; VCC = 4.5 V to 5.5 V; CL = 50 pF; Tamb -40 C to +125 C | 8 |
| propagation delay E1, E2 to Yn | tpd | 1 | 4.3 | 12 | ns | E1, E2 to Yn; see Figure 7; VCC = 4.5 V to 5.5 V; CL = 15 pF; Tamb -40 C to +125 C | 8 |
| propagation delay E1, E2 to Yn | tpd | 1 | 6.2 | 13.5 | ns | E1, E2 to Yn; see Figure 7; VCC = 4.5 V to 5.5 V; CL = 50 pF; Tamb -40 C to +125 C | 8 |
## CAD (KiCad official)
- Symbol: `74AHCT138PW`
- Footprint: `Package_SO:TSSOP-16_4.4x5mm_P0.65mm`
- 3D model: TSSOP-16 (KiCad packages3D, STEP)
- 3D model files: `74ahct138pw-etched.step` / `74ahct138pw-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `74ahct138pw.step` / `74ahct138pw.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Nexperia datasheet](https://assets.nexperia.com/documents/data-sheet/74AHCT138PW.pdf) (17 pp, sha256 `63520b5b696b050e`, retrieved 2026-10-18, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/74ahct138pw-datasheet.pdf)