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74AHCT00S14-13
Public Made by Adomby adom
Diodes Incorporated Logic Gates, SO-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by adom_assets · KiCad file format 20240108
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74AHCT00S14-13
Diodes Incorporated · Logic Gates · SO-14
74AHCT00S14-13 from Diodes Incorporated, in a SO-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1A | input | Data input 1A of NAND gate 1, TTL voltage-level compatible with Schmitt trigger action and a recommended input voltage range of 0 to 5.5 V. |
| 2 | 1B | input | Data input 1B of NAND gate 1, TTL voltage-level compatible with Schmitt trigger action and a recommended input voltage range of 0 to 5.5 V. |
| 3 | 1Y | output | Data output 1Y of NAND gate 1, a standard push-pull output that sinks or sources 8 mA at VCC = 4.5 V. |
| 4 | 2A | input | Data input 2A of NAND gate 2, TTL voltage-level compatible with Schmitt trigger action and a recommended input voltage range of 0 to 5.5 V. |
| 5 | 2B | input | Data input 2B of NAND gate 2, TTL voltage-level compatible with Schmitt trigger action and a recommended input voltage range of 0 to 5.5 V. |
| 6 | 2Y | output | Data output 2Y of NAND gate 2, a standard push-pull output that sinks or sources 8 mA at VCC = 4.5 V. |
| 7 | GND | power_in | Ground reference; unused inputs should be held at VCC or ground, and continuous current through GND is limited to -50 mA. |
| 8 | 3Y | output | Data output 3Y of NAND gate 3, a standard push-pull output that sinks or sources 8 mA at VCC = 4.5 V. |
| 9 | 3A | input | Data input 3A of NAND gate 3, TTL voltage-level compatible with Schmitt trigger action and a recommended input voltage range of 0 to 5.5 V. |
| 10 | 3B | input | Data input 3B of NAND gate 3, TTL voltage-level compatible with Schmitt trigger action and a recommended input voltage range of 0 to 5.5 V. |
| 11 | 4Y | output | Data output 4Y of NAND gate 4, a standard push-pull output that sinks or sources 8 mA at VCC = 4.5 V. |
| 12 | 4A | input | Data input 4A of NAND gate 4, TTL voltage-level compatible with Schmitt trigger action and a recommended input voltage range of 0 to 5.5 V. |
| 13 | 4B | input | Data input 4B of NAND gate 4, TTL voltage-level compatible with Schmitt trigger action and a recommended input voltage range of 0 to 5.5 V. |
| 14 | VCC | power_in | Supply voltage, recommended range 4.5 V to 5.5 V, with absolute maximum rating of -0.5 to +7.0 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Diodes Incorporated |
| Package | SO-14 |
| Category | Logic |
| Pins | 14 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply Voltage | VCC | 4.5 | 5.5 | V | 3 | ||
| Input Voltage | VI | 0 | 5.5 | V | 3 | ||
| Output Voltage | VO | 0 | V | max printed as VCC | 3 | ||
| Input Transition Rise or Fall Rate | Δt/ΔV | 20 | ns/V | 3 | |||
| Operating Free-Air Temperature | TA | -40 | 125 | °C | 3 | ||
| ESD Protection Human Body Model | ESD HBM | 2 | KV | 2 | |||
| ESD Protection Charged Device Model | ESD CDM | 1 | KV | 2 | |||
| ESD Protection Machine Model | ESD MM | 200 | V | 2 | |||
| Supply Voltage Range | VCC | -0.5 | 7 | V | 2 | ||
| Input Voltage Range | VI | -0.5 | 7 | V | 2 | ||
| Input Clamp Current | IIK | -20 | mA | VI < -0.5V | 2 | ||
| Output Clamp Current | IOK | -20 | mA | VO < 0V | 2 | ||
| Output Clamp Current | IOK | 20 | mA | VO > VCC | 2 | ||
| Continuous Output Current | IO | -25 | 25 | mA | 0V < VO < VCC | 2 | |
| Continuous Current Through VCC | ICC | 50 | mA | 2 | |||
| Continuous Current Through GND | IGND | -50 | mA | 2 | |||
| Operating Junction Temperature | TJ | -40 | 150 | °C | 2 | ||
| Storage Temperature | TSTG | -65 | 150 | °C | 2 | ||
| Total Power Dissipation | PTOT | 500 | mW | 2 | |||
| High-Level Input Voltage | VIH | 2 | V | VCC 4.5V to 5.5V | 3 | ||
| Low-Level Input Voltage | VIL | 0.8 | V | VCC 4.5V to 5.5V | 3 | ||
| High-Level Output Voltage | VOH | 4.4 | V | IOH = -50μA, VCC 4.5V | 3 | ||
| High-Level Output Voltage | VOH | 3.8 | V | IOH = -8mA, VCC 4.5V, TA = -40°C to +85°C | 3 | ||
| High-Level Output Voltage | VOH | 3.7 | V | IOH = -8mA, VCC 4.5V, TA = -40°C to +125°C | 3 | ||
| Low-Level Output Voltage | VOL | 0.1 | V | IOL = 50μA, VCC 4.5V | 3 | ||
| Low-Level Output Voltage | VOL | 0.44 | V | IOL = 8mA, VCC 4.5V, TA = -40°C to +85°C | 3 | ||
| Low-Level Output Voltage | VOL | 0.55 | V | IOL = 8mA, VCC 4.5V, TA = -40°C to +125°C | 3 | ||
| Input Current | II | -1 | 1 | μA | VI = GND to 5.5V, VCC 3.6V, TA = -40°C to +85°C | 3 | |
| Input Current | II | -2 | 2 | μA | VI = GND to 5.5V, VCC 3.6V, TA = -40°C to +125°C | 3 | |
| Supply Current | ICC | 20 | μA | VI = GND or VCC, IO = 0, VCC 3.6V, TA = -40°C to +85°C | 3 | ||
| Supply Current | ICC | 40 | μA | VI = GND or VCC, IO = 0, VCC 3.6V, TA = -40°C to +125°C | 3 | ||
| Additional Supply Current | ΔICC | 1.35 | mA | One input at VCC -2.1V, other pins at VCC or GND, VCC 5.5V, TA = -40°C to +85°C | 3 | ||
| Additional Supply Current | ΔICC | 5 | mA | One input at VCC -2.1V, other pins at VCC or GND, VCC 5.5V, TA = -40°C to +125°C | 3 | ||
| Power dissipation capacitance per gate | Cpd | 14.8 | pF | f = 1MHz, VCC = 5.5V | 3 | ||
| Input Capacitance | Ci | 4 | pF | Vi = VCC, or GND | 3 | ||
| Propagation Delay AN to YN | tPD | 0.5 | 3.4 | 6.9 | ns | Figure 1, CL = 15pF, VCC 4.5V to 5.5V, TA = +25°C | 3 |
| Propagation Delay AN to YN | tPD | 0.5 | 8 | ns | Figure 1, CL = 15pF, VCC 4.5V to 5.5V, TA = -40°C to +85°C | 3 | |
| Propagation Delay AN to YN | tPD | 0.5 | 9 | ns | Figure 1, CL = 15pF, VCC 4.5V to 5.5V, TA = -40°C to +125°C | 3 | |
| Propagation Delay AN to YN | tPD | 0.5 | 4.9 | 10 | ns | Figure 1, CL = 50pF, VCC 4.5V to 5.5V, TA = +25°C | 3 |
| Propagation Delay AN to YN | tPD | 0.5 | 10 | ns | Figure 1, CL = 50pF, VCC 4.5V to 5.5V, TA = -40°C to +85°C | 3 | |
| Propagation Delay AN to YN | tPD | 0.5 | 11 | ns | Figure 1, CL = 50pF, VCC 4.5V to 5.5V, TA = -40°C to +125°C | 3 |
CAD (KiCad official)
- Symbol:
74AHCT00S14-13 - Footprint:
Adom_Gen:Diodes_Incorporated_74 - 3D model: SO-14 (KiCad packages3D, STEP)
- 3D model files:
74ahct00s14-13-etched.step/74ahct00s14-13-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);74ahct00s14-13.step/74ahct00s14-13.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Diodes Incorporated datasheet (8 pp, sha256
35924409ee5734b3, retrieved 2026-10-27, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusoff(skipped (clean text read)), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).