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74AHC595T16-13
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Diodes Incorporated Registers, TSSOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
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74AHC595T16-13
Diodes Incorporated · Registers · TSSOP-16
74AHC595T16-13 from Diodes Incorporated, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | Q1 | tri_state | Parallel 3-state data output 1, active when OE is asserted low. |
| 2 | Q2 | tri_state | Parallel 3-state data output 2, active when OE is asserted low. |
| 3 | Q3 | tri_state | Parallel 3-state data output 3, active when OE is asserted low. |
| 4 | Q4 | tri_state | Parallel 3-state data output 4, active when OE is asserted low. |
| 5 | Q5 | tri_state | Parallel 3-state data output 5, active when OE is asserted low. |
| 6 | Q6 | tri_state | Parallel 3-state data output 6, active when OE is asserted low. |
| 7 | Q7 | tri_state | Parallel 3-state data output 7, active when OE is asserted low. |
| 8 | GND | power_in | Ground reference for the device. |
| 9 | Q7S | output | Serial data output; the content of Q6S is shifted to Q7S and appears on this pin. |
| 10 | MR | input | Master reset input; when asserted low it sets all shift register values to zero and is independent of all clocks. |
| 11 | SHCP | input | Shift register clock input; data on DS is shifted in on each positive transition of this clock. |
| 12 | STCP | input | Storage register clock input; a rising pulse transfers the shift register contents to the output register. |
| 13 | OE | input | Output enable input; the 3-state outputs Q0-Q7 become active when asserted low. |
| 14 | DS | input | Serial data input, captured on each positive transition of the shift register clock. |
| 15 | Q0 | tri_state | Parallel 3-state data output 0, active when OE is asserted low. |
| 16 | VCC | power_in | Supply voltage, recommended range 2.0 V to 5.5 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Diodes Incorporated |
| Package | TSSOP-16 |
| Category | Logic ICs |
| Pins | 16 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply Voltage | VCC | 2 | 5.5 | V | 4 | ||
| Input Voltage | VI | 0 | 5.5 | V | 4 | ||
| Output Voltage | VO | 0 | V | Active Mode; printed maximum is VCC | 4 | ||
| Input transition rise or fall rate | Δt/ΔV | 100 | ns/V | VCC = 3.0V to 3.6V | 4 | ||
| Input transition rise or fall rate | Δt/ΔV | 20 | ns/V | VCC = 4.5V to 5.5V | 4 | ||
| Operating Free-Air Temperature | TA | -40 | 125 | °C | 4 | ||
| Supply Voltage Range | VCC | -0.5 | 7 | V | 4 | ||
| Input Voltage Range | VI | -0.5 | 7 | V | 4 | ||
| Voltage applied to output in high or low state | Vo | -0.3 | V | printed maximum is VCC +0.5 V | 4 | ||
| Input Clamp Current | IIK | -20 | mA | VI < -0.5V | 4 | ||
| Output Clamp Current | IOK | -20 | mA | VO <-0.5V | 4 | ||
| Output Clamp Current | IOK | 25 | mA | VO > VCC + 0.5V | 4 | ||
| Continuous output current | IO | -25 | 25 | mA | 4 | ||
| Continuous current through Vcc or GND | ICC | 75 | mA | 4 | |||
| Continuous current through Vcc or GND (GND) | IGND | -75 | mA | 4 | |||
| Operating Junction Temperature | TJ | -40 | 150 | °C | 4 | ||
| Storage Temperature | TSTG | -65 | 150 | °C | 4 | ||
| Total Power Dissipation | PTOT | 500 | mW | 4 | |||
| High-level Input Voltage | VIH | 1.5 | V | VCC = 2.0V | 4 | ||
| High-level Input Voltage | VIH | 2.1 | V | VCC = 3.0V | 4 | ||
| High-level Input Voltage | VIH | 3.85 | V | VCC = 5.5V | 4 | ||
| Low-level input voltage | VIL | 0.5 | V | VCC = 2.0V | 4 | ||
| Low-level input voltage | VIL | 0.9 | V | VCC = 3.0V | 4 | ||
| Low-level input voltage | VIL | 1.65 | V | VCC = 5.5V | 4 | ||
| High Level Output Voltage | VOH | 1.9 | 2 | V | IOH = -50μA; VCC = 2.0V | 4 | |
| High Level Output Voltage | VOH | 2.9 | 3 | V | IOH = -50μA; VCC = 3.0V | 4 | |
| High Level Output Voltage | VOH | 4.4 | 4.5 | V | IOH = -50μA; VCC = 4.5V | 4 | |
| High Level Output Voltage | VOH | 2.4 | V | IOH = -4mA; VCC = 3.0V | 4 | ||
| High Level Output Voltage | VOH | 3.7 | V | IOH = -8mA; VCC = 4.5V | 4 | ||
| Low-level Output Voltage | VOL | 0 | 0.1 | V | IOL = 50μA; VCC = 2.0V | 4 | |
| Low-level Output Voltage | VOL | 0.55 | V | IOL = 4mA; VCC = 3.0V | 4 | ||
| Input Current | II | -2 | 0.1 | 2 | μA | VI = GND to 5.5V; VCC = 5.5V | 4 |
| OFF-state output current | IOZ | -10 | 10 | μA | VI = VIH or VIL; VO = VCC or GND; VCC = 5.5V | 4 | |
| Supply Current | ICC | 80 | μA | VI = GND or VCC; IO = 0; VCC = 5.5V | 4 | ||
| Fmax Maximum Frequency SHCP or STCP | fMAX | 40 | 125 | MHz | Figure 2; VCC = 3.0V to 3.6V | 5 | |
| Fmax Maximum Frequency SHCP or STCP | fMAX | 90 | MHz | Figure 2; VCC = 4.5V to 5.5V | 5 | ||
| Set-up Time DS to SHCP | tSU | 3.5 | ns | Figure 2; VCC = 3.0V to 3.6V | 5 | ||
| Set-up Time DS to SHCP | tSU | 3 | ns | Figure 2; VCC = 4.5V to 5.5V | 5 | ||
| Set-up Time SHCP to STCP | tSU | 8.5 | ns | Figure 2; VCC = 3.0V to 3.6V | 5 | ||
| Set-up Time SHCP to STCP | tSU | 5 | ns | Figure 2; VCC = 4.5V to 5.5V | 5 | ||
| Hold Time DS to SHCP | tH | 1.5 | ns | Figure 2; VCC = 3.0V to 3.6V | 5 | ||
| Hold Time DS to SHCP | tH | 2 | ns | Figure 2; VCC = 4.5V to 5.5V | 5 | ||
| Recovery Time MR to SHCP | tREC | 3 | ns | Figure 2; VCC = 3.0V to 3.6V | 5 | ||
| Recovery Time MR to SHCP | tREC | 2.5 | ns | Figure 2; VCC = 4.5V to 5.5V | 5 | ||
| Propagation Delay SHCP to Q7S | tPD | 1 | 5.7 | 16.5 | ns | Figure 2; CL = 15pF; VCC = 3.0V to 3.6V | 5 |
| Propagation Delay SHCP to Q7S | tPD | 1 | 4 | 10.5 | ns | Figure 2; CL = 15pF; VCC = 4.5V to 5.5V | 5 |
| Propagation Delay SHCP to Q7S | tPD | 1 | 7.7 | 20.1 | ns | Figure 2; CL = 50pF; VCC = 3.0V to 3.6V | 5 |
| Propagation Delay SHCP to Q7S | tPD | 1 | 5.4 | 12.5 | ns | Figure 2; CL = 50pF; VCC = 4.5V to 5.5V | 5 |
| Propagation Delay STCP to Qn | tPD | 1 | 5.9 | 15 | ns | Figure 2; CL = 15pF; VCC = 3.0V to 3.6V | 5 |
| Propagation Delay STCP to Qn | tPD | 1 | 4.2 | 10.5 | ns | Figure 2; CL = 15pF; VCC = 4.5V to 5.5V | 5 |
| Propagation Delay STCP to Qn | tPD | 1 | 7.7 | 18.5 | ns | Figure 2; CL = 50pF; VCC = 3.0V to 3.6V | 5 |
| Propagation Delay STCP to Qn | tPD | 1 | 5.5 | 11.5 | ns | Figure 2; CL = 50pF; VCC = 4.5V to 5.5V | 5 |
| Propagation Delay MR to Q7S | tPD | 1 | 5.9 | 15 | ns | Figure 2; CL = 15pF; VCC = 3.0V to 3.6V | 5 |
| Propagation Delay MR to Q7S | tPD | 1 | 4.4 | 10.5 | ns | Figure 2; CL = 15pF; VCC = 4.5 V to 5.5V | 5 |
| Enable Time OE to Qn | tEN | 1 | 5.6 | 15 | ns | Figure 2; CL = 15pF; VCC = 3.0V to 3.6V | 5 |
| Enable Time OE to Qn | tEN | 1 | 4 | 10.5 | ns | Figure 2; CL = 15pF; VCC = 4.5V to 5.5V | 5 |
| Disable Time OE to Qn | tDIS | 1 | 5.4 | 14.5 | ns | Figure 2; CL = 15pF; VCC = 3.0V to 3.6V | 5 |
CAD (KiCad official)
- Symbol:
74AHC595T16-13 - Footprint:
Package_SO:TSSOP-16_4.4x5mm_P0.65mm - 3D model: TSSOP-16 (KiCad packages3D, STEP)
- 3D model files:
74ahc595t16-13-etched.step/74ahc595t16-13-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);74ahc595t16-13.step/74ahc595t16-13.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Diodes Incorporated datasheet (10 pp, sha256
ed9a25b6f7409598, retrieved 2026-10-27, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).