component

74AHC595D

Public Made by Adom

by adom

Nexperia Shift Registers, SOIC-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentlogic74ahc595dfactory-2.0.0extractor-text
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity
main
74ahc595d / README.md
History Download
Ray Publish 0.1.0 08aabf8 19h ago

74AHC595D

Nexperia · Shift Registers · SOIC-16

74AHC595D from Nexperia, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 Q1 tri_state Parallel data output Q1 of the storage register; it is in the high-impedance OFF-state when OE is HIGH.
2 Q2 tri_state Parallel data output Q2 of the storage register; it is in the high-impedance OFF-state when OE is HIGH.
3 Q3 tri_state Parallel data output Q3 of the storage register; it is in the high-impedance OFF-state when OE is HIGH.
4 Q4 tri_state Parallel data output Q4 of the storage register; it is in the high-impedance OFF-state when OE is HIGH.
5 Q5 tri_state Parallel data output Q5 of the storage register; it is in the high-impedance OFF-state when OE is HIGH.
6 Q6 tri_state Parallel data output Q6 of the storage register; it is in the high-impedance OFF-state when OE is HIGH.
7 Q7 tri_state Parallel data output Q7 of the storage register; it is in the high-impedance OFF-state when OE is HIGH.
8 GND power_in Ground (0 V) reference for all voltages on the device.
9 Q7S output Serial data output Q7S, which passes the shift register stage 7 state for cascading to another device.
10 MR input Asynchronous master reset input, active LOW; a LOW level resets the shift register.
11 SHCP input Shift register clock input; data is shifted on the LOW-to-HIGH transition of SHCP.
12 STCP input Storage register clock input; data is transferred to the storage register on the LOW-to-HIGH transition of STCP.
13 OE input Output enable input, active LOW; a HIGH level forces the Qn outputs into the high-impedance OFF-state.
14 DS input Serial data input to the 8-bit shift register.
15 Q0 tri_state Parallel data output Q0 of the storage register; it is in the high-impedance OFF-state when OE is HIGH.
16 VCC power_in Supply voltage, 2.0 V to 5.5 V for the 74AHC595 (Table 5).

Key specifications

Parameter Value
Manufacturer Nexperia
Package SOIC-16
Category Logic
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
supply voltage VCC -0.5 7 V 6
input voltage VI -0.5 7 V 6
input clamping current IIK -20 mA VI < -0.5 V 6
output clamping current IOK -20 20 mA VO < -0.5 V or VO > VCC + 0.5 V 6
output current IO -25 25 mA VO = -0.5 V to (VCC + 0.5 V) 6
supply current ICC 75 mA 6
ground current IGND -75 mA 6
storage temperature Tstg -65 150 °C 6
total power dissipation Ptot 500 mW Tamb = -40 °C to +125 °C 6
supply voltage VCC 2 5 5.5 V 6
input voltage VI 0 5.5 V 6
output voltage VO 0 V 6
ambient temperature Tamb -40 25 125 °C 6
input transition rise and fall rate Δt/ΔV 100 ns/V VCC = 3.0 V to 3.6 V 6
input transition rise and fall rate Δt/ΔV 20 ns/V VCC = 4.5 V to 5.5 V 6
HIGH-level input voltage VIH 1.5 V VCC = 2.0 V 6
HIGH-level input voltage VIH 2.1 V VCC = 3.0 V 6
HIGH-level input voltage VIH 3.85 V VCC = 5.5 V 6
LOW-level input voltage VIL 0.5 V VCC = 2.0 V 6
LOW-level input voltage VIL 0.9 V VCC = 3.0 V 6
LOW-level input voltage VIL 1.65 V VCC = 5.5 V 6
HIGH-level output voltage VOH 1.9 2 V VI = VIH or VIL; IO = -50 μA; VCC = 2.0 V 7
HIGH-level output voltage VOH 2.9 3 V VI = VIH or VIL; IO = -50 μA; VCC = 3.0 V 7
HIGH-level output voltage VOH 4.4 4.5 V VI = VIH or VIL; IO = -50 μA; VCC = 4.5 V 7
HIGH-level output voltage VOH 2.58 V VI = VIH or VIL; IO = -4.0 mA; VCC = 3.0 V 7
HIGH-level output voltage VOH 3.94 V VI = VIH or VIL; IO = -8.0 mA; VCC = 4.5 V 7
LOW-level output voltage VOL 0 0.1 V VI = VIH or VIL; IO = 50 μA; VCC = 2.0 V 7
LOW-level output voltage VOL 0.36 V VI = VIH or VIL; IO = 4.0 mA; VCC = 3.0 V 7
input leakage current II 0.1 μA VI = 5.5 V or GND; VCC = 0 V to 5.5 V 7
OFF-state output current IOZ -0.25 0.25 μA VI = VIH or VIL; VO = VCC or GND; VCC = 5.5 V 7
supply current ICC 4 μA VI = VCC or GND; IO = 0 A; VCC = 5.5 V 7
input capacitance CI 3 10 pF 7
propagation delay tpd 1 5.7 13 ns SHCP to Q7S; VCC = 3.0 V to 3.6 V; CL = 15 pF 8
propagation delay tpd 1 7.7 16.5 ns SHCP to Q7S; VCC = 3.0 V to 3.6 V; CL = 50 pF 8
propagation delay tpd 1 4 8.2 ns SHCP to Q7S; VCC = 4.5 V to 5.5 V; CL = 15 pF 8
propagation delay tpd 1 5.4 10 ns SHCP to Q7S; VCC = 4.5 V to 5.5 V; CL = 50 pF 8
propagation delay tpd 1 5.9 11.9 ns STCP to Qn; VCC = 3.0 V to 3.6 V; CL = 15 pF 8
propagation delay tpd 1 7.7 15.4 ns STCP to Qn; VCC = 3.0 V to 3.6 V; CL = 50 pF 8
propagation delay tpd 1 4.2 7.4 ns STCP to Qn; VCC = 4.5 V to 5.5 V; CL = 15 pF 8
propagation delay tpd 1 5.5 9 ns STCP to Qn; VCC = 4.5 V to 5.5 V; CL = 50 pF 8
HIGH to LOW propagation delay tPHL 1 5.9 12.8 ns MR to Q7S; VCC = 3.0 V to 3.6 V; CL = 15 pF 8
HIGH to LOW propagation delay tPHL 1 7.4 16.3 ns MR to Q7S; VCC = 3.0 V to 3.6 V; CL = 50 pF 8
HIGH to LOW propagation delay tPHL 1 4.4 8 ns MR to Q7S; VCC = 4.5 V to 5.5 V; CL = 15 pF 8
HIGH to LOW propagation delay tPHL 1 5.6 10 ns MR to Q7S; VCC = 4.5 V to 5.5 V; CL = 50 pF 8
enable time ten 1 5.6 11.5 ns OE to Qn; VCC = 3.0 V to 3.6 V; CL = 15 pF 8
enable time ten 1 7.4 15 ns OE to Qn; VCC = 3.0 V to 3.6 V; CL = 50 pF 8
enable time ten 1 4 8.6 ns OE to Qn; VCC = 4.5 V to 5.5 V; CL = 15 pF 8
enable time ten 1 5.3 10.6 ns OE to Qn; VCC = 4.5 V to 5.5 V; CL = 50 pF 8
disable time tdis 1 5.4 11 ns OE to Qn; VCC = 3.0 V to 3.6 V; CL = 15 pF 8
disable time tdis 1 8.7 15.7 ns OE to Qn; VCC = 3.0 V to 3.6 V; CL = 50 pF 8
disable time tdis 1 3.8 8 ns OE to Qn; VCC = 4.5 V to 5.5 V; CL = 15 pF 8
disable time tdis 1 5.8 10.3 ns OE to Qn; VCC = 4.5 V to 5.5 V; CL = 50 pF 8
maximum frequency fmax 80 125 MHz SHCP or STCP; see Fig. 6 and Fig. 7; VCC = 3.0 V to 3.6 V 8
maximum frequency fmax 130 170 MHz SHCP or STCP; see Fig. 6 and Fig. 7; VCC = 4.5 V to 5.5 V 8
pulse width tW 5 ns SHCP HIGH or LOW; see Fig. 6; VCC = 3.0 V to 3.6 V 8
set-up time tsu 3.5 ns DS to SHCP; see Fig. 8; VCC = 3.0 V to 3.6 V 9
set-up time tsu 3 ns DS to SHCP; see Fig. 8; VCC = 4.5 V to 5.5 V 9
set-up time tsu 8.5 ns SHCP to STCP; see Fig. 7; VCC = 3.0 V to 3.6 V 9
set-up time tsu 5 ns SHCP to STCP; see Fig. 7; VCC = 4.5 V to 5.5 V 9
hold time th 1.5 ns DS to SHCP; see Fig. 8; VCC = 3.0 V to 3.6 V 9
hold time th 2 ns DS to SHCP; see Fig. 8; VCC = 4.5 V to 5.5 V 9
recovery time trec 3 ns MR to SHCP; see Fig. 9; VCC = 3.0 V to 3.6 V 9
recovery time trec 2.5 ns MR to SHCP; see Fig. 9; VCC = 4.5 V to 5.5 V 9
power dissipation capacitance CPD 180 pF fi = 1 MHz; VI = GND to VCC 9

CAD (KiCad official)

  • Symbol: 74AHC595D
  • Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
  • 3D model: SOIC-16 (KiCad packages3D, STEP)
  • 3D model files: 74ahc595d-etched.step / 74ahc595d-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); 74ahc595d.step / 74ahc595d.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Nexperia datasheet (19 pp, sha256 67d6cf86d0a75a0a, retrieved 2026-10-27, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed (audit)), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF