component

74AHC595BQ

Public Made by Adom

by adom

Nexperia Shift Registers, DHVQFN-16-EP(2.5x3.5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentlogic74ahc595bqfactory-2.0.0extractor-text
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity
main
Download ZIP Propose a change
Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 6d ago
viewers 74ahc595bq: viewers · Ray 6d ago
74ahc595bq-etched.glb Publish 0.1.0 · Ray 6d ago
74ahc595bq-etched.step 74ahc595bq: factory component page (tier=mfr) · Ray 6d ago
74ahc595bq-hero.glb 74ahc595bq: hero GLB from the etched model (keeps the MPN mark) · Ray 6d ago
74ahc595bq-hero.overlay.json Publish 0.1.0 · Ray 6d ago
74ahc595bq.glb Publish 0.1.0 · Ray 6d ago
74ahc595bq.kicad_mod Publish 0.1.0 · Ray 6d ago
74ahc595bq.kicad_sym Publish 0.1.0 · Ray 6d ago
74ahc595bq.lbr Publish 0.1.0 · Ray 6d ago
74ahc595bq.step Publish 0.1.0 · Ray 6d ago
package.json Publish 0.1.0 · Ray 6d ago
page.json Set visibility: public · Ray 6d ago
README.md Publish 0.1.0 · Ray 6d ago

74AHC595BQ

Nexperia · Shift Registers · DHVQFN-16-EP(2.5x3.5)

74AHC595BQ from Nexperia, in a DHVQFN-16-EP(2.5x3.5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 Q1 tri_state Parallel data output Q1 of the storage register; it goes to high-impedance OFF-state when OE is HIGH.
2 Q2 tri_state Parallel data output Q2 of the storage register; it goes to high-impedance OFF-state when OE is HIGH.
3 Q3 tri_state Parallel data output Q3 of the storage register; it goes to high-impedance OFF-state when OE is HIGH.
4 Q4 tri_state Parallel data output Q4 of the storage register; it goes to high-impedance OFF-state when OE is HIGH.
5 Q5 tri_state Parallel data output Q5 of the storage register; it goes to high-impedance OFF-state when OE is HIGH.
6 Q6 tri_state Parallel data output Q6 of the storage register; it goes to high-impedance OFF-state when OE is HIGH.
7 Q7 tri_state Parallel data output Q7 of the storage register; it goes to high-impedance OFF-state when OE is HIGH.
8 GND power_in Ground (0 V) reference for all voltages; absolute maximum ground current is -75 mA.
9 Q7S output Serial data output Q7S, used for cascading; it reflects the shift register stage 7 contents.
10 MR input Asynchronous master reset, active LOW; a LOW level resets the shift register.
11 SHCP input Shift register clock input; data is shifted on the LOW-to-HIGH transition.
12 STCP input Storage register clock input; data is transferred to the storage register on the LOW-to-HIGH transition.
13 OE input Output enable input, active LOW; a HIGH level forces the outputs to high-impedance OFF-state.
14 DS input Serial data input to the 8-bit shift register.
15 Q0 tri_state Parallel data output Q0 of the storage register; it goes to high-impedance OFF-state when OE is HIGH.
16 VCC power_in Supply voltage; recommended range is 2.0 V to 5.5 V for 74AHC595 and 4.5 V to 5.5 V for 74AHCT595.
17 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Nexperia
Package DHVQFN-16-EP(2.5x3.5)
Category Logic
Pins 17

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VCC -0.5 7 V 6
Input voltage VI -0.5 7 V 6
Input clamping current IIK -20 mA VI < -0.5 V 6
Output clamping current IOK -20 20 mA VO < -0.5 V or VO > VCC + 0.5 V 6
Output current IO -25 25 mA VO = -0.5 V to (VCC + 0.5 V) 6
Supply current ICC 75 mA 6
Ground current IGND -75 mA 6
Storage temperature Tstg -65 150 °C 6
Total power dissipation Ptot 500 mW Tamb = -40 °C to +125 °C 6
Supply voltage VCC 2 5 5.5 V 6
Input voltage VI 0 5.5 V 6
Output voltage VO 0 V 6
Ambient temperature Tamb -40 25 125 °C 6
Input transition rise and fall rate Δt/ΔV 100 ns/V VCC = 3.0 V to 3.6 V 6
Input transition rise and fall rate Δt/ΔV 20 ns/V VCC = 4.5 V to 5.5 V 6
HIGH-level input voltage VIH 1.5 V VCC = 2.0 V 6
HIGH-level input voltage VIH 2.1 V VCC = 3.0 V 6
HIGH-level input voltage VIH 3.85 V VCC = 5.5 V 6
LOW-level input voltage VIL 0.5 V VCC = 2.0 V 6
LOW-level input voltage VIL 0.9 V VCC = 3.0 V 6
LOW-level input voltage VIL 1.65 V VCC = 5.5 V 6
HIGH-level output voltage VOH 1.9 2 V VI = VIH or VIL; IO = -50 μA; VCC = 2.0 V 7
HIGH-level output voltage VOH 2.9 3 V VI = VIH or VIL; IO = -50 μA; VCC = 3.0 V 7
HIGH-level output voltage VOH 4.4 4.5 V VI = VIH or VIL; IO = -50 μA; VCC = 4.5 V 7
HIGH-level output voltage VOH 2.4 V VI = VIH or VIL; IO = -4.0 mA; VCC = 3.0 V 7
HIGH-level output voltage VOH 3.7 V VI = VIH or VIL; IO = -8.0 mA; VCC = 4.5 V 7
LOW-level output voltage VOL 0 0.1 V VI = VIH or VIL; IO = 50 μA; VCC = 2.0 V 7
LOW-level output voltage VOL 0.55 V VI = VIH or VIL; IO = 4.0 mA; VCC = 3.0 V 7
Input leakage current II 2 μA VI = 5.5 V or GND; VCC = 0 V to 5.5 V 7
OFF-state output current IOZ -10 10 μA VI = VIH or VIL; VO = VCC or GND; VCC = 5.5 V 7
Supply current ICC 80 μA VI = VCC or GND; IO = 0 A; VCC = 5.5 V 7
Input capacitance CI 3 10 pF 7
Propagation delay SHCP to Q7S tpd 1 5.7 16.5 ns VCC = 3.0 V to 3.6 V; CL = 15 pF 8
Propagation delay SHCP to Q7S tpd 1 7.7 20.1 ns VCC = 3.0 V to 3.6 V; CL = 50 pF 8
Propagation delay SHCP to Q7S tpd 1 4 10.5 ns VCC = 4.5 V to 5.5 V; CL = 15 pF 8
Propagation delay SHCP to Q7S tpd 1 5.4 12.5 ns VCC = 4.5 V to 5.5 V; CL = 50 pF 8
Propagation delay STCP to Qn tpd 1 5.9 15 ns VCC = 3.0 V to 3.6 V; CL = 15 pF 8
Propagation delay STCP to Qn tpd 1 7.7 18.5 ns VCC = 3.0 V to 3.6 V; CL = 50 pF 8
Propagation delay STCP to Qn tpd 1 4.2 9.5 ns VCC = 4.5 V to 5.5 V; CL = 15 pF 8
Propagation delay STCP to Qn tpd 1 5.5 11.5 ns VCC = 4.5 V to 5.5 V; CL = 50 pF 8
Propagation delay MR to Q7S tPHL 1 5.9 15 ns VCC = 3.0 V to 3.6 V; CL = 15 pF 8
Propagation delay MR to Q7S tPHL 1 4.4 10 ns VCC = 4.5 V to 5.5 V; CL = 15 pF 8
Propagation delay MR to Q7S tPHL 1 5.6 12 ns VCC = 4.5 V to 5.5 V; CL = 50 pF 8
Enable time OE to Qn ten 1 5.6 15 ns VCC = 3.0 V to 3.6 V; CL = 15 pF 8
Enable time OE to Qn ten 1 7.4 18.5 ns VCC = 3.0 V to 3.6 V; CL = 50 pF 8
Enable time OE to Qn ten 1 4 11 ns VCC = 4.5 V to 5.5 V; CL = 15 pF 8
Enable time OE to Qn ten 1 5.3 13 ns VCC = 4.5 V to 5.5 V; CL = 50 pF 8
Maximum frequency SHCP or STCP fmax 80 125 MHz VCC = 3.0 V to 3.6 V 8
Maximum frequency SHCP or STCP fmax 130 170 MHz VCC = 4.5 V to 5.5 V 8
SHCP pulse width HIGH or LOW tW 5 ns VCC = 3.0 V to 3.6 V 8
STCP pulse width HIGH or LOW tW 5 ns VCC = 3.0 V to 3.6 V 8
Set-up time DS to SHCP tsu 3.5 ns VCC = 3.0 V to 3.6 V 9
Set-up time DS to SHCP tsu 3 ns VCC = 4.5 V to 5.5 V 9
Set-up time SHCP to STCP tsu 8.5 ns VCC = 3.0 V to 3.6 V 9
Set-up time SHCP to STCP tsu 5 ns VCC = 4.5 V to 5.5 V 9

CAD (KiCad official)

  • Symbol: 74AHC595BQ
  • Footprint: Package_DFN_QFN:DHVQFN-16-1EP_2.5x3.5mm_P0.5mm_EP1x2mm
  • 3D model: DHVQFN-16-EP(2.5x3.5), generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 0.9 mm nominal VQFN height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
  • 3D model files: 74ahc595bq-etched.step / 74ahc595bq-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); 74ahc595bq.step / 74ahc595bq.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Nexperia datasheet (19 pp, sha256 67d6cf86d0a75a0a, retrieved 2026-10-16, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF