component
74AHC594PW
Public Made by Adomby adom
Nexperia Shift Registers, TSSOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdown74AHC594PW
Nexperia · Shift Registers · TSSOP-16
74AHC594PW from Nexperia, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | Q1 | output | Parallel data output Q1 of the 8-bit storage register. |
| 2 | Q2 | output | Parallel data output Q2 of the 8-bit storage register. |
| 3 | Q3 | output | Parallel data output Q3 of the 8-bit storage register. |
| 4 | Q4 | output | Parallel data output Q4 of the 8-bit storage register. |
| 5 | Q5 | output | Parallel data output Q5 of the 8-bit storage register. |
| 6 | Q6 | output | Parallel data output Q6 of the 8-bit storage register. |
| 7 | Q7 | output | Parallel data output Q7 of the 8-bit storage register. |
| 8 | GND | power_in | Ground (0 V) reference for all voltages. |
| 9 | Q7S | output | Serial data output Q7S of the shift register, provided for cascading purposes. |
| 10 | SHR | input | Shift register reset input, active LOW; a LOW on SHR only affects the shift register. |
| 11 | SHCP | input | Shift register clock input; the shift register is positive-edge triggered. |
| 12 | STCP | input | Storage register clock input; the storage register is positive-edge triggered. |
| 13 | STR | input | Storage register reset input, active LOW; a LOW on STR only affects the storage register. |
| 14 | DS | input | Serial data input to the shift register; inputs are overvoltage tolerant to 5.5 V. |
| 15 | Q0 | output | Parallel data output Q0 of the 8-bit storage register. |
| 16 | VCC | power_in | Supply voltage: 2.0 V to 5.5 V for 74AHC594 and 4.5 V to 5.5 V for 74AHCT594. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Nexperia |
| Package | TSSOP-16 |
| Category | Logic |
| Pins | 16 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage | VCC | -0.5 | 7 | V | 5 | ||
| Input voltage | VI | -0.5 | 7 | V | 5 | ||
| Input clamping current | IIK | -20 | mA | VI < -0.5 V | 5 | ||
| Output clamping current | IOK | -20 | 20 | mA | VO < -0.5 V or VO > VCC + 0.5 V | 5 | |
| Output current | IO | -25 | 25 | mA | VO = -0.5 V to (VCC + 0.5 V) | 5 | |
| Supply current | ICC | 75 | mA | 5 | |||
| Ground current | IGND | -75 | mA | 5 | |||
| Storage temperature | Tstg | -65 | 150 | °C | 5 | ||
| Total power dissipation | Ptot | 500 | mW | Tamb = -40 °C to +125 °C | 5 | ||
| Supply voltage (74AHC594) | VCC | 2 | 5 | 5.5 | V | 6 | |
| Input voltage | VI | 0 | 5.5 | V | 6 | ||
| Output voltage | VO | 0 | V | 6 | |||
| Ambient temperature | Tamb | -40 | 25 | 125 | °C | 6 | |
| Input transition rise and fall rate | Δt/ΔV | 100 | ns/V | VCC = 3.0 V to 3.6 V | 6 | ||
| Input transition rise and fall rate | Δt/ΔV | 20 | ns/V | VCC = 4.5 V to 5.5 V | 6 | ||
| HIGH-level input voltage | VIH | 1.5 | V | -40 °C to +125 °C; VCC = 2.0 V | 6 | ||
| HIGH-level input voltage | VIH | 2.1 | V | -40 °C to +125 °C; VCC = 3.0 V | 6 | ||
| HIGH-level input voltage | VIH | 3.85 | V | -40 °C to +125 °C; VCC = 5.5 V | 6 | ||
| LOW-level input voltage | VIL | 0.5 | V | -40 °C to +125 °C; VCC = 2.0 V | 6 | ||
| LOW-level input voltage | VIL | 0.9 | V | -40 °C to +125 °C; VCC = 3.0 V | 6 | ||
| LOW-level input voltage | VIL | 1.65 | V | -40 °C to +125 °C; VCC = 5.5 V | 6 | ||
| HIGH-level output voltage | VOH | 1.9 | 2 | V | VI = VIH or VIL; IO = -50 μA; VCC = 2.0 V; -40 °C to +125 °C | 6 | |
| HIGH-level output voltage | VOH | 2.9 | 3 | V | VI = VIH or VIL; IO = -50 μA; VCC = 3.0 V; -40 °C to +125 °C | 6 | |
| HIGH-level output voltage | VOH | 4.4 | 4.5 | V | VI = VIH or VIL; IO = -50 μA; VCC = 4.5 V; -40 °C to +125 °C | 6 | |
| HIGH-level output voltage | VOH | 2.4 | V | VI = VIH or VIL; IO = -4.0 mA; VCC = 3.0 V; -40 °C to +125 °C | 6 | ||
| HIGH-level output voltage | VOH | 3.7 | V | VI = VIH or VIL; IO = -8.0 mA; VCC = 4.5 V; -40 °C to +125 °C | 6 | ||
| LOW-level output voltage | VOL | 0 | 0.1 | V | VI = VIH or VIL; IO = 50 μA; VCC = 2.0 V; -40 °C to +125 °C | 6 | |
| LOW-level output voltage | VOL | 0.55 | V | VI = VIH or VIL; IO = 4 mA; VCC = 3.0 V; -40 °C to +125 °C | 6 | ||
| Input leakage current | II | 2 | μA | VI = 5.5 V or GND; VCC = 0 V to 5.5 V; -40 °C to +125 °C | 6 | ||
| Supply current | ICC | 80 | μA | VI = VCC or GND; IO = 0 A; VCC = 5.5 V; -40 °C to +125 °C | 6 | ||
| Input capacitance | CI | 3 | 10 | pF | VI = VCC or GND | 6 | |
| LOW to HIGH propagation delay, SHCP to Q7S | tPLH | 3 | 7.4 | 14.3 | ns | see Fig. 6; VCC = 3.0 V to 3.6 V; CL = 50 pF; -40 °C to +125 °C | 7 |
| LOW to HIGH propagation delay, SHCP to Q7S | tPLH | 2.4 | 4.8 | 10 | ns | see Fig. 6; VCC = 4.5 V to 5.5 V; CL = 50 pF; -40 °C to +125 °C | 7 |
| LOW to HIGH propagation delay, STCP to Qn | tPLH | 3.3 | 7.3 | 14.7 | ns | see Fig. 7; VCC = 3.0 V to 3.6 V; CL = 50 pF; -40 °C to +125 °C | 7 |
| LOW to HIGH propagation delay, STCP to Qn | tPLH | 2.6 | 4.8 | 9.8 | ns | see Fig. 7; VCC = 4.5 V to 5.5 V; CL = 50 pF; -40 °C to +125 °C | 7 |
| HIGH to LOW propagation delay, SHCP to Q7S | tPHL | 3 | 7.4 | 15.1 | ns | see Fig. 6; VCC = 3.0 V to 3.6 V; CL = 50 pF; -40 °C to +125 °C | 8 |
| HIGH to LOW propagation delay, SHCP to Q7S | tPHL | 2.5 | 5.4 | 11 | ns | see Fig. 6; VCC = 4.5 V to 5.5 V; CL = 50 pF; -40 °C to +125 °C | 8 |
| HIGH to LOW propagation delay, STCP to Qn | tPHL | 3.2 | 7.3 | 15 | ns | see Fig. 7; VCC = 3.0 V to 3.6 V; CL = 50 pF; -40 °C to +125 °C | 8 |
| HIGH to LOW propagation delay, STCP to Qn | tPHL | 2.6 | 5.2 | 10.5 | ns | see Fig. 7; VCC = 4.5 V to 5.5 V; CL = 50 pF; -40 °C to +125 °C | 8 |
| HIGH to LOW propagation delay, SHR to Q7S | tPHL | 3.6 | 7.5 | 15.2 | ns | see Fig. 10; VCC = 3.0 V to 3.6 V; CL = 50 pF; -40 °C to +125 °C | 8 |
| HIGH to LOW propagation delay, SHR to Q7S | tPHL | 2.8 | 5.4 | 11 | ns | see Fig. 10; VCC = 4.5 V to 5.5 V; CL = 50 pF; -40 °C to +125 °C | 8 |
| HIGH to LOW propagation delay, STR to Qn | tPHL | 3.8 | 7.7 | 15.6 | ns | see Fig. 9; VCC = 3.0 V to 3.6 V; CL = 50 pF; -40 °C to +125 °C | 8 |
| HIGH to LOW propagation delay, STR to Qn | tPHL | 3 | 5.4 | 11.6 | ns | see Fig. 9; VCC = 4.5 V to 5.5 V; CL = 50 pF; -40 °C to +125 °C | 8 |
| Maximum frequency | fmax | 65 | 125 | MHz | SHCP or STCP; see Fig. 6 and Fig. 7; VCC = 3.0 V to 3.6 V; -40 °C to +125 °C | 8 | |
| Maximum frequency | fmax | 70 | 170 | MHz | SHCP or STCP; see Fig. 6 and Fig. 7; VCC = 4.5 V to 5.5 V; -40 °C to +125 °C | 8 | |
| Set-up time, DS to SHCP | tsu | 4 | ns | see Fig. 8; VCC = 3.0 V to 3.6 V; -40 °C to +125 °C | 9 | ||
| Set-up time, DS to SHCP | tsu | 3.5 | ns | see Fig. 8; VCC = 4.5 V to 5.5 V; -40 °C to +125 °C | 9 | ||
| Set-up time, SHR to STCP | tsu | 9.5 | ns | see Fig. 11; VCC = 3.0 V to 3.6 V; -40 °C to +125 °C | 9 | ||
| Set-up time, SHR to STCP | tsu | 5.5 | ns | see Fig. 11; VCC = 4.5 V to 5.5 V; -40 °C to +125 °C | 9 | ||
| Set-up time, SHCP to STCP | tsu | 9 | ns | see Fig. 7; VCC = 3.0 V to 3.6 V; -40 °C to +125 °C | 9 | ||
| Set-up time, SHCP to STCP | tsu | 5.5 | ns | see Fig. 7; VCC = 4.5 V to 5.5 V; -40 °C to +125 °C | 9 | ||
| Hold time, DS to SHCP | th | 2 | ns | see Fig. 8; VCC = 3.0 V to 3.6 V; -40 °C to +125 °C | 9 | ||
| Hold time, DS to SHCP | th | 2.5 | ns | see Fig. 8; VCC = 4.5 V to 5.5 V; -40 °C to +125 °C | 9 | ||
| Recovery time, SHR to SHCP | trec | 5.3 | ns | see Fig. 10; VCC = 3.0 V to 3.6 V; -40 °C to +125 °C | 9 | ||
| Recovery time, SHR to SHCP | trec | 3.8 | ns | see Fig. 10; VCC = 4.5 V to 5.5 V; -40 °C to +125 °C | 9 | ||
| Recovery time, STR to STCP | trec | 5.8 | ns | see Fig. 9; VCC = 3.0 V to 3.6 V; -40 °C to +125 °C | 9 | ||
| Recovery time, STR to STCP | trec | 4.3 | ns | see Fig. 9; VCC = 4.5 V to 5.5 V; -40 °C to +125 °C | 9 |
CAD (KiCad official)
- Symbol:
74AHC594PW - Footprint:
Package_SO:TSSOP-16_4.4x5mm_P0.65mm - 3D model: TSSOP-16 (KiCad packages3D, STEP)
- 3D model files:
74ahc594pw-etched.step/74ahc594pw-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);74ahc594pw.step/74ahc594pw.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Nexperia datasheet (19 pp, sha256
904f218d5c3a23ea, retrieved 2026-10-18, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).