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74AHC573BQ

Nexperia · Latches · DHVQFN-20(2.5x4.5)

74AHC573BQ from Nexperia, in a DHVQFN-20(2.5x4.5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 OE input Output enable input (active LOW); a HIGH level puts outputs Q0 to Q7 into the high-impedance OFF-state and does not affect the latch contents.
2 D0 input Data input for latch 0; inputs are overvoltage tolerant to 5.5 V and have Schmitt-trigger action.
3 D1 input Data input for latch 1; inputs are overvoltage tolerant to 5.5 V and have Schmitt-trigger action.
4 D2 input Data input for latch 2; inputs are overvoltage tolerant to 5.5 V and have Schmitt-trigger action.
5 D3 input Data input for latch 3; inputs are overvoltage tolerant to 5.5 V and have Schmitt-trigger action.
6 D4 input Data input for latch 4; inputs are overvoltage tolerant to 5.5 V and have Schmitt-trigger action.
7 D5 input Data input for latch 5; inputs are overvoltage tolerant to 5.5 V and have Schmitt-trigger action.
8 D6 input Data input for latch 6; inputs are overvoltage tolerant to 5.5 V and have Schmitt-trigger action.
9 D7 input Data input for latch 7; inputs are overvoltage tolerant to 5.5 V and have Schmitt-trigger action.
10 GND power_in Ground (0 V); all voltages in the datasheet are referenced to this pin.
11 LE input Latch enable input (active HIGH); when HIGH the latches are transparent, and when LOW they store the data present at the inputs.
12 Q7 tri_state 3-state data output of latch 7; high-impedance when OE is HIGH, with output current limited to ±25 mA.
13 Q6 tri_state 3-state data output of latch 6; high-impedance when OE is HIGH, with output current limited to ±25 mA.
14 Q5 tri_state 3-state data output of latch 5; high-impedance when OE is HIGH, with output current limited to ±25 mA.
15 Q4 tri_state 3-state data output of latch 4; high-impedance when OE is HIGH, with output current limited to ±25 mA.
16 Q3 tri_state 3-state data output of latch 3; high-impedance when OE is HIGH, with output current limited to ±25 mA.
17 Q2 tri_state 3-state data output of latch 2; high-impedance when OE is HIGH, with output current limited to ±25 mA.
18 Q1 tri_state 3-state data output of latch 1; high-impedance when OE is HIGH, with output current limited to ±25 mA.
19 Q0 tri_state 3-state data output of latch 0; high-impedance when OE is HIGH, with output current limited to ±25 mA.
20 VCC power_in Supply voltage; 2.0 V to 5.5 V for 74AHC573 and 4.5 V to 5.5 V for 74AHCT573, with an absolute maximum of 7.0 V.
21 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Nexperia
Package DHVQFN-20(2.5x4.5)
Category Logic
Pins 21

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VCC -0.5 7 V 5
Input voltage VI -0.5 7 V 5
Input clamping current IIK -20 mA VI < -0.5 V 5
Output clamping current IOK -20 20 mA VO < -0.5 V or VO > VCC + 0.5 V 5
Output current IO -25 25 mA VO = -0.5 V to (VCC + 0.5 V) 5
Supply current ICC 75 mA 5
Ground current IGND -75 mA 5
Storage temperature Tstg -65 150 °C 5
Total power dissipation Ptot 500 mW Tamb = -40 °C to +125 °C 5
Supply voltage VCC 2 5 5.5 V 74AHC573 5
Input voltage VI 0 5.5 V 74AHC573 5
Output voltage VO 0 V 74AHC573; max printed as VCC 5
Ambient temperature Tamb -40 25 125 °C 74AHC573 5
Input transition rise and fall rate Δt/ΔV 100 ns/V VCC = 3.3 V ± 0.3 V 5
Input transition rise and fall rate Δt/ΔV 20 ns/V VCC = 5.0 V ± 0.5 V 5
HIGH-level input voltage VIH 1.5 V VCC = 2.0 V; limits at -40 °C to +125 °C 6
HIGH-level input voltage VIH 2.1 V VCC = 3.0 V; limits at -40 °C to +125 °C 6
HIGH-level input voltage VIH 3.85 V VCC = 5.5 V; limits at -40 °C to +125 °C 6
LOW-level input voltage VIL 0.5 V VCC = 2.0 V; limits at -40 °C to +125 °C 6
LOW-level input voltage VIL 0.9 V VCC = 3.0 V; limits at -40 °C to +125 °C 6
LOW-level input voltage VIL 1.65 V VCC = 5.5 V; limits at -40 °C to +125 °C 6
HIGH-level output voltage VOH 1.9 2 V VI = VIH or VIL; IO = -50 μA; VCC = 2.0 V; limits at -40 °C to +125 °C 6
HIGH-level output voltage VOH 2.9 3 V VI = VIH or VIL; IO = -50 μA; VCC = 3.0 V; limits at -40 °C to +125 °C 6
HIGH-level output voltage VOH 4.4 4.5 V VI = VIH or VIL; IO = -50 μA; VCC = 4.5 V; limits at -40 °C to +125 °C 6
HIGH-level output voltage VOH 2.4 V VI = VIH or VIL; IO = -4.0 mA; VCC = 3.0 V; limits at -40 °C to +125 °C 6
HIGH-level output voltage VOH 3.7 V VI = VIH or VIL; IO = -8.0 mA; VCC = 4.5 V; limits at -40 °C to +125 °C 6
LOW-level output voltage VOL 0 0.1 V VI = VIH or VIL; IO = 50 μA; VCC = 2.0 V; limits at -40 °C to +125 °C 6
LOW-level output voltage VOL 0.55 V VI = VIH or VIL; IO = 4.0 mA; VCC = 3.0 V; limits at -40 °C to +125 °C 6
OFF-state output current IOZ -10 10 μA VI = VIH or VIL; VO = VCC or GND; VCC = 5.5 V; limits at -40 °C to +125 °C 6
Input leakage current II 2 μA VI = VCC or GND; VCC = 0 V to 5.5 V; limits at -40 °C to +125 °C 6
Supply current ICC 80 μA VI = VCC or GND; IO = 0 A; VCC = 5.5 V; limits at -40 °C to +125 °C 6
Input capacitance CI 3 10 pF VI = VCC or GND; max at -40 °C to +125 °C 6
Output capacitance CO 4 10 pF max at -40 °C to +125 °C 6
Propagation delay Dn to Qn tpd 1 5.5 14 ns VCC = 3.0 V to 3.6 V; CL = 15 pF; see Fig. 5; limits at -40 °C to +125 °C 8
Propagation delay Dn to Qn tpd 1 7.8 18.5 ns VCC = 3.0 V to 3.6 V; CL = 50 pF; see Fig. 5; limits at -40 °C to +125 °C 8
Propagation delay Dn to Qn tpd 1 3.9 8.5 ns VCC = 4.5 V to 5.5 V; CL = 15 pF; see Fig. 5; limits at -40 °C to +125 °C 8
Propagation delay Dn to Qn tpd 1 5.5 11 ns VCC = 4.5 V to 5.5 V; CL = 50 pF; see Fig. 5; limits at -40 °C to +125 °C 8
Propagation delay LE to Qn tpd 1 5.8 15 ns VCC = 3.0 V to 3.6 V; CL = 15 pF; see Fig. 6; limits at -40 °C to +125 °C 8
Propagation delay LE to Qn tpd 1 8.3 19.5 ns VCC = 3.0 V to 3.6 V; CL = 50 pF; see Fig. 6; limits at -40 °C to +125 °C 8
Propagation delay LE to Qn tpd 1 4.2 10 ns VCC = 4.5 V to 5.5 V; CL = 15 pF; see Fig. 6; limits at -40 °C to +125 °C 8
Propagation delay LE to Qn tpd 1 5.9 12.5 ns VCC = 4.5 V to 5.5 V; CL = 50 pF; see Fig. 6; limits at -40 °C to +125 °C 8
Enable time OE to Qn ten 1 5.8 14.5 ns VCC = 3.0 V to 3.6 V; CL = 15 pF; see Fig. 7; limits at -40 °C to +125 °C 8
Enable time OE to Qn ten 1 8.3 19 ns VCC = 3.0 V to 3.6 V; CL = 50 pF; see Fig. 7; limits at -40 °C to +125 °C 8
Enable time OE to Qn ten 1 4.4 10 ns VCC = 4.5 V to 5.5 V; CL = 15 pF; see Fig. 7; limits at -40 °C to +125 °C 8
Enable time OE to Qn ten 1 6.3 12.5 ns VCC = 4.5 V to 5.5 V; CL = 50 pF; see Fig. 7; limits at -40 °C to +125 °C 8
Disable time OE to Qn tdis 1 6.8 14 ns VCC = 3.0 V to 3.6 V; CL = 15 pF; see Fig. 7; limits at -40 °C to +125 °C 8
Disable time OE to Qn tdis 1 9.7 18.5 ns VCC = 3.0 V to 3.6 V; CL = 50 pF; see Fig. 7; limits at -40 °C to +125 °C 8
Disable time OE to Qn tdis 1 4.6 10 ns VCC = 4.5 V to 5.5 V; CL = 15 pF; see Fig. 7; limits at -40 °C to +125 °C 8
Disable time OE to Qn tdis 1 7.4 12.5 ns VCC = 4.5 V to 5.5 V; CL = 50 pF; see Fig. 7; limits at -40 °C to +125 °C 8
Pulse width LE HIGH tW 5 ns VCC = 3.0 V to 3.6 V; LE HIGH; see Fig. 6; limits at -40 °C to +125 °C 8
Set-up time Dn to LE tsu 3.5 ns VCC = 3.0 V to 3.6 V; Dn to LE; see Fig. 8; limits at -40 °C to +125 °C 8
Hold time Dn to LE th 1.5 ns VCC = 3.0 V to 3.6 V; Dn to LE; see Fig. 8; limits at -40 °C to +125 °C 8

CAD (KiCad official)

  • Symbol: 74AHC573BQ
  • Footprint: Package_DFN_QFN:DHVQFN-20-1EP_2.5x4.5mm_P0.5mm_EP1x3mm
  • 3D model: DHVQFN-20(2.5x4.5), generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 0.9 mm nominal VQFN height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
  • 3D model files: 74ahc573bq-etched.step / 74ahc573bq-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); 74ahc573bq.step / 74ahc573bq.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Nexperia datasheet (17 pp, sha256 70a39eb3d8b5f2b1, retrieved 2026-10-19, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF