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74AHC373PW

Public Made by Adom

by adom

Nexperia Latches, TSSOP-20. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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74AHC373PW

Nexperia · Latches · TSSOP-20

74AHC373PW from Nexperia, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 OE input 3-state output enable input, active LOW; a HIGH on OE forces the Q outputs to the high-impedance OFF-state without changing the latch contents.
2 Q0 tri_state 3-state latch output 0, which goes to high-impedance when OE is HIGH.
3 D0 input Data input 0 to the latch; inputs are overvoltage tolerant to 5.5 V and accept voltages higher than VCC.
4 D1 input Data input 1 to the latch; inputs are overvoltage tolerant to 5.5 V and accept voltages higher than VCC.
5 Q1 tri_state 3-state latch output 1, which goes to high-impedance when OE is HIGH.
6 Q2 tri_state 3-state latch output 2, which goes to high-impedance when OE is HIGH.
7 D2 input Data input 2 to the latch; inputs are overvoltage tolerant to 5.5 V and accept voltages higher than VCC.
8 D3 input Data input 3 to the latch; inputs are overvoltage tolerant to 5.5 V and accept voltages higher than VCC.
9 Q3 tri_state 3-state latch output 3, which goes to high-impedance when OE is HIGH.
10 GND power_in Ground reference at 0 V.
11 LE input Latch enable input, active HIGH; the latches are transparent while LE is HIGH and store the input on the HIGH-to-LOW transition of LE.
12 Q4 tri_state 3-state latch output 4, which goes to high-impedance when OE is HIGH.
13 D4 input Data input 4 to the latch; inputs are overvoltage tolerant to 5.5 V and accept voltages higher than VCC.
14 D5 input Data input 5 to the latch; inputs are overvoltage tolerant to 5.5 V and accept voltages higher than VCC.
15 Q5 tri_state 3-state latch output 5, which goes to high-impedance when OE is HIGH.
16 Q6 tri_state 3-state latch output 6, which goes to high-impedance when OE is HIGH.
17 D6 input Data input 6 to the latch; inputs are overvoltage tolerant to 5.5 V and accept voltages higher than VCC.
18 D7 input Data input 7 to the latch; inputs are overvoltage tolerant to 5.5 V and accept voltages higher than VCC.
19 Q7 tri_state 3-state latch output 7, which goes to high-impedance when OE is HIGH.
20 VCC power_in Supply voltage; recommended operating range is 2.0 V to 5.5 V with a typical value of 5.0 V.

Key specifications

Parameter Value
Manufacturer Nexperia
Package TSSOP-20
Category Logic
Pins 20

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage (absolute maximum) VCC -0.5 7 V 4
Input voltage (absolute maximum) VI -0.5 7 V 4
Input clamping current IIK -20 mA VI < -0.5 V 4
Output clamping current IOK -20 20 mA VO < -0.5 V or VO > VCC + 0.5 V 4
Output current IO -25 25 mA VO = -0.5 V to (VCC + 0.5 V) 4
Supply current ICC 75 mA 4
Ground current IGND -75 mA 4
Storage temperature Tstg -65 150 °C 4
Total power dissipation Ptot 500 mW Tamb = -40 °C to +125 °C 4
Supply voltage (recommended) VCC 2 5 5.5 V 4
Input voltage (recommended) VI 0 5.5 V 4
Output voltage (recommended) VO 0 V 4
Ambient temperature Tamb -40 25 125 °C 4
Input transition rise and fall rate Δt/ΔV 100 ns/V VCC = 3.0 V to 3.6 V 4
Input transition rise and fall rate Δt/ΔV 20 ns/V VCC = 4.5 V to 5.5 V 4
HIGH-level input voltage VIH 1.5 V VCC = 2.0 V 5
HIGH-level input voltage VIH 2.1 V VCC = 3.0 V 5
HIGH-level input voltage VIH 3.85 V VCC = 5.5 V 5
LOW-level input voltage VIL 0.5 V VCC = 2.0 V 5
LOW-level input voltage VIL 0.9 V VCC = 3.0 V 5
LOW-level input voltage VIL 1.65 V VCC = 5.5 V 5
HIGH-level output voltage VOH 1.9 2 V VI = VIH or VIL; IO = -50 μA; VCC = 2.0 V 5
HIGH-level output voltage VOH 2.9 3 V VI = VIH or VIL; IO = -50 μA; VCC = 3.0 V 5
HIGH-level output voltage VOH 4.4 4.5 V VI = VIH or VIL; IO = -50 μA; VCC = 4.5 V 5
HIGH-level output voltage VOH 2.4 V VI = VIH or VIL; IO = -4.0 mA; VCC = 3.0 V 5
HIGH-level output voltage VOH 3.7 V VI = VIH or VIL; IO = -8.0 mA; VCC = 4.5 V 5
LOW-level output voltage VOL 0 0.1 V VI = VIH or VIL; IO = 50 μA; VCC = 2.0 V 5
LOW-level output voltage VOL 0.55 V VI = VIH or VIL; IO = 4.0 mA; VCC = 3.0 V 5
OFF-state output current IOZ -10 10 μA VI = VIH or VIL; VO = VCC or GND; VCC = 5.5 V 5
Input leakage current II 2 μA VI = VCC or GND; VCC = 0 V to 5.5 V 5
Supply current ICC 80 μA VI = VCC or GND; IO = 0 A; VCC = 5.5 V 5
Input capacitance CI 3 10 pF VI = VCC or GND 5
Output capacitance CO 4 10 pF 5
Propagation delay Dn to Qn tpd 1 6 14.5 ns Dn to Qn; VCC = 3.0 V to 3.6 V; CL = 15 pF 6
Propagation delay Dn to Qn tpd 1 7.8 19 ns Dn to Qn; VCC = 3.0 V to 3.6 V; CL = 50 pF 6
Propagation delay Dn to Qn tpd 1 4 9 ns Dn to Qn; VCC = 4.5 V to 5.5 V; CL = 15 pF 6
Propagation delay Dn to Qn tpd 1 5.3 11.5 ns Dn to Qn; VCC = 4.5 V to 5.5 V; CL = 50 pF 6
Propagation delay LE to Qn tpd 1 6.3 14 ns LE to Qn; VCC = 3.0 V to 3.6 V; CL = 15 pF 6
Propagation delay LE to Qn tpd 1 8.3 18.5 ns LE to Qn; VCC = 3.0 V to 3.6 V; CL = 50 pF 6
Propagation delay LE to Qn tpd 1 4.3 9 ns LE to Qn; VCC = 4.5 V to 5.5 V; CL = 15 pF 6
Propagation delay LE to Qn tpd 1 5.6 12.5 ns LE to Qn; VCC = 4.5 V to 5.5 V; CL = 50 pF 6
Enable time OE to Qn ten 1 5.6 14.5 ns OE to Qn; VCC = 3.0 V to 3.6 V; CL = 15 pF 6
Enable time OE to Qn ten 1 7.5 19 ns OE to Qn; VCC = 3.0 V to 3.6 V; CL = 50 pF 6
Enable time OE to Qn ten 1 3.8 10.5 ns OE to Qn; VCC = 4.5 V to 5.5 V; CL = 15 pF 6
Enable time OE to Qn ten 1 5.2 13 ns OE to Qn; VCC = 4.5 V to 5.5 V; CL = 50 pF 6
Disable time OE to Qn tdis 1 5.6 13 ns OE to Qn; VCC = 3.0 V to 3.6 V; CL = 15 pF 6
Disable time OE to Qn tdis 1 9.2 17 ns OE to Qn; VCC = 3.0 V to 3.6 V; CL = 50 pF 6
Disable time OE to Qn tdis 1 4.3 9.5 ns OE to Qn; VCC = 4.5 V to 5.5 V; CL = 15 pF 6
Disable time OE to Qn tdis 1 6.4 11.5 ns OE to Qn; VCC = 4.5 V to 5.5 V; CL = 50 pF 6
Pulse width tW 5 ns LE HIGH or LOW; VCC = 3.0 V to 3.6 V 6
Set-up time tsu 4 ns Dn to LE; VCC = 3.0 V to 3.6 V 6
Hold time th 1 ns Dn to LE; VCC = 3.0 V to 3.6 V 6
Total power dissipation derating (SOT360-1 TSSOP20) Ptot 10 mW/K Derates linearly above 100 °C 4

CAD (KiCad official)

  • Symbol: 74AHC373PW
  • Footprint: Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm
  • 3D model: TSSOP-20 (KiCad packages3D, STEP)
  • 3D model files: 74ahc373pw-etched.step / 74ahc373pw-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); 74ahc373pw.step / 74ahc373pw.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Nexperia datasheet (13 pp, sha256 9545b42f56ced51e, retrieved 2026-10-21, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF