component
74AHC32PW
Public Made by Adomby adom
Nexperia Gates, TSSOP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
main
74AHC32PW
Nexperia · Gates · TSSOP-14
74AHC32PW from Nexperia, in a TSSOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1A | input | Data input 1A of gate 1; with 1B it forms the OR function 1Y = 1A + 1B (Table 3). |
| 2 | 1B | input | Data input 1B of gate 1; with 1A it forms the OR function 1Y = 1A + 1B (Table 3). |
| 3 | 1Y | output | Data output 1Y of gate 1, HIGH when either 1A or 1B is HIGH (Table 3). |
| 4 | 2A | input | Data input 2A of gate 2; with 2B it forms the OR function 2Y = 2A + 2B (Table 3). |
| 5 | 2B | input | Data input 2B of gate 2; with 2A it forms the OR function 2Y = 2A + 2B (Table 3). |
| 6 | 2Y | output | Data output 2Y of gate 2, HIGH when either 2A or 2B is HIGH (Table 3). |
| 7 | GND | power_in | Ground pin (0 V) for the device; all voltages are referenced to GND (Table 2 and Table 4). |
| 8 | 3Y | output | Data output 3Y of gate 3, HIGH when either 3A or 3B is HIGH (Table 3). |
| 9 | 3A | input | Data input 3A of gate 3; with 3B it forms the OR function 3Y = 3A + 3B (Table 3). |
| 10 | 3B | input | Data input 3B of gate 3; with 3A it forms the OR function 3Y = 3A + 3B (Table 3). |
| 11 | 4Y | output | Data output 4Y of gate 4, HIGH when either 4A or 4B is HIGH (Table 3). |
| 12 | 4A | input | Data input 4A of gate 4; with 4B it forms the OR function 4Y = 4A + 4B (Table 3). |
| 13 | 4B | input | Data input 4B of gate 4; with 4A it forms the OR function 4Y = 4A + 4B (Table 3). |
| 14 | VCC | power_in | Supply voltage; recommended range is 2.0 V to 5.5 V for 74AHC32 and 4.5 V to 5.5 V for 74AHCT32 (Table 5). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Nexperia |
| Package | TSSOP-14 |
| Category | Logic ICs |
| Pins | 14 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage (absolute maximum) | VCC | -0.5 | 7 | V | 3 | ||
| Input voltage (absolute maximum) | VI | -0.5 | 7 | V | 3 | ||
| Input clamping current | IIK | -20 | mA | VI < -0.5 V | 3 | ||
| Output clamping current | IOK | -20 | 20 | mA | VO < -0.5 V or VO > VCC + 0.5 V | 3 | |
| Output current | IO | -25 | 25 | mA | VO = -0.5 V to (VCC + 0.5 V) | 3 | |
| Supply current | ICC | 75 | mA | 3 | |||
| Ground current | IGND | -75 | mA | 3 | |||
| Storage temperature | Tstg | -65 | 150 | °C | 3 | ||
| Total power dissipation | Ptot | 500 | mW | Tamb = -40 °C to +125 °C; SOT402-1 (TSSOP14) derates 7.3 mW/K above 81 °C | 3 | ||
| Supply voltage (recommended) | VCC | 2 | 5 | 5.5 | V | 4 | |
| Input voltage (recommended) | VI | 0 | 5.5 | V | 4 | ||
| Output voltage (recommended) | VO | 0 | V | 4 | |||
| Ambient temperature | Tamb | -40 | 25 | 125 | °C | 4 | |
| Input transition rise and fall rate | Δt/ΔV | 100 | ns/V | VCC = 3.0 V to 3.6 V | 4 | ||
| Input transition rise and fall rate | Δt/ΔV | 20 | ns/V | VCC = 4.5 V to 5.5 V | 4 | ||
| HIGH-level input voltage | VIH | 1.5 | V | VCC = 2.0 V; 25 °C | 4 | ||
| HIGH-level input voltage | VIH | 2.1 | V | VCC = 3.0 V; 25 °C | 4 | ||
| HIGH-level input voltage | VIH | 3.85 | V | VCC = 5.5 V; 25 °C | 4 | ||
| LOW-level input voltage | VIL | 0.5 | V | VCC = 2.0 V; 25 °C | 4 | ||
| LOW-level input voltage | VIL | 0.9 | V | VCC = 3.0 V; 25 °C | 4 | ||
| LOW-level input voltage | VIL | 1.65 | V | VCC = 5.5 V; 25 °C | 4 | ||
| HIGH-level output voltage | VOH | 1.9 | 2 | V | VI = VIH or VIL; IO = -50 μA; VCC = 2.0 V; 25 °C | 4 | |
| HIGH-level output voltage | VOH | 1.9 | V | VI = VIH or VIL; IO = -50 μA; VCC = 2.0 V; -40 °C to +125 °C | 4 | ||
| HIGH-level output voltage | VOH | 2.9 | 3 | V | VI = VIH or VIL; IO = -50 μA; VCC = 3.0 V; 25 °C | 4 | |
| HIGH-level output voltage | VOH | 2.9 | V | VI = VIH or VIL; IO = -50 μA; VCC = 3.0 V; -40 °C to +125 °C | 4 | ||
| HIGH-level output voltage | VOH | 4.4 | 4.5 | V | VI = VIH or VIL; IO = -50 μA; VCC = 4.5 V; 25 °C | 4 | |
| HIGH-level output voltage | VOH | 4.4 | V | VI = VIH or VIL; IO = -50 μA; VCC = 4.5 V; -40 °C to +125 °C | 4 | ||
| HIGH-level output voltage | VOH | 2.58 | V | VI = VIH or VIL; IO = -4.0 mA; VCC = 3.0 V; 25 °C | 4 | ||
| HIGH-level output voltage | VOH | 2.4 | V | VI = VIH or VIL; IO = -4.0 mA; VCC = 3.0 V; -40 °C to +125 °C | 4 | ||
| HIGH-level output voltage | VOH | 3.94 | V | VI = VIH or VIL; IO = -8.0 mA; VCC = 4.5 V; 25 °C | 4 | ||
| HIGH-level output voltage | VOH | 3.7 | V | VI = VIH or VIL; IO = -8.0 mA; VCC = 4.5 V; -40 °C to +125 °C | 4 | ||
| LOW-level output voltage | VOL | 0 | 0.1 | V | VI = VIH or VIL; IO = 50 μA; VCC = 2.0 V; 25 °C | 4 | |
| LOW-level output voltage | VOL | 0.1 | V | VI = VIH or VIL; IO = 50 μA; VCC = 2.0 V; -40 °C to +125 °C | 4 | ||
| LOW-level output voltage | VOL | 0.36 | V | VI = VIH or VIL; IO = 4.0 mA; VCC = 3.0 V; 25 °C | 4 | ||
| LOW-level output voltage | VOL | 0.55 | V | VI = VIH or VIL; IO = 4.0 mA; VCC = 3.0 V; -40 °C to +125 °C | 4 | ||
| Input leakage current | II | 0.1 | μA | VI = 5.5 V or GND; VCC = 0 V to 5.5 V; 25 °C | 4 | ||
| Input leakage current | II | 2 | μA | VI = 5.5 V or GND; VCC = 0 V to 5.5 V; -40 °C to +125 °C | 4 | ||
| Supply current | ICC | 2 | μA | VI = VCC or GND; IO = 0 A; VCC = 5.5 V; 25 °C | 4 | ||
| Supply current | ICC | 40 | μA | VI = VCC or GND; IO = 0 A; VCC = 5.5 V; -40 °C to +125 °C | 4 | ||
| Input capacitance | CI | 3 | 10 | pF | VI = VCC or GND; 25 °C | 4 | |
| Propagation delay | tpd | 3.9 | 7.9 | ns | nA, nB to nY; VCC = 3.0 V to 3.6 V; CL = 15 pF; 25 °C | 5 | |
| Propagation delay | tpd | 1 | 10 | ns | nA, nB to nY; VCC = 3.0 V to 3.6 V; CL = 15 pF; -40 °C to +125 °C | 5 | |
| Propagation delay | tpd | 5.6 | 11.4 | ns | nA, nB to nY; VCC = 3.0 V to 3.6 V; CL = 50 pF; 25 °C | 5 | |
| Propagation delay | tpd | 1 | 14.5 | ns | nA, nB to nY; VCC = 3.0 V to 3.6 V; CL = 50 pF; -40 °C to +125 °C | 5 | |
| Propagation delay | tpd | 2.8 | 5.5 | ns | nA, nB to nY; VCC = 4.5 V to 5.5 V; CL = 15 pF; 25 °C | 5 | |
| Propagation delay | tpd | 1 | 7 | ns | nA, nB to nY; VCC = 4.5 V to 5.5 V; CL = 15 pF; -40 °C to +125 °C | 5 | |
| Propagation delay | tpd | 4.1 | 7.5 | ns | nA, nB to nY; VCC = 4.5 V to 5.5 V; CL = 50 pF; 25 °C | 5 | |
| Propagation delay | tpd | 1 | 9.5 | ns | nA, nB to nY; VCC = 4.5 V to 5.5 V; CL = 50 pF; -40 °C to +125 °C | 5 |
CAD (KiCad official)
- Symbol:
74AHC32PW - Footprint:
Package_SO:TSSOP-14_4.4x5mm_P0.65mm - 3D model: TSSOP-14 (KiCad packages3D, STEP)
- 3D model files:
74ahc32pw-etched.step/74ahc32pw-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);74ahc32pw.step/74ahc32pw.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Nexperia datasheet (13 pp, sha256
71f897a7a0bfa4c3, retrieved 2026-10-28, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# 74AHC32PW
**Nexperia** · Gates · TSSOP-14
74AHC32PW from Nexperia, in a TSSOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1A | input | Data input 1A of gate 1; with 1B it forms the OR function 1Y = 1A + 1B (Table 3). |
| 2 | 1B | input | Data input 1B of gate 1; with 1A it forms the OR function 1Y = 1A + 1B (Table 3). |
| 3 | 1Y | output | Data output 1Y of gate 1, HIGH when either 1A or 1B is HIGH (Table 3). |
| 4 | 2A | input | Data input 2A of gate 2; with 2B it forms the OR function 2Y = 2A + 2B (Table 3). |
| 5 | 2B | input | Data input 2B of gate 2; with 2A it forms the OR function 2Y = 2A + 2B (Table 3). |
| 6 | 2Y | output | Data output 2Y of gate 2, HIGH when either 2A or 2B is HIGH (Table 3). |
| 7 | GND | power_in | Ground pin (0 V) for the device; all voltages are referenced to GND (Table 2 and Table 4). |
| 8 | 3Y | output | Data output 3Y of gate 3, HIGH when either 3A or 3B is HIGH (Table 3). |
| 9 | 3A | input | Data input 3A of gate 3; with 3B it forms the OR function 3Y = 3A + 3B (Table 3). |
| 10 | 3B | input | Data input 3B of gate 3; with 3A it forms the OR function 3Y = 3A + 3B (Table 3). |
| 11 | 4Y | output | Data output 4Y of gate 4, HIGH when either 4A or 4B is HIGH (Table 3). |
| 12 | 4A | input | Data input 4A of gate 4; with 4B it forms the OR function 4Y = 4A + 4B (Table 3). |
| 13 | 4B | input | Data input 4B of gate 4; with 4A it forms the OR function 4Y = 4A + 4B (Table 3). |
| 14 | VCC | power_in | Supply voltage; recommended range is 2.0 V to 5.5 V for 74AHC32 and 4.5 V to 5.5 V for 74AHCT32 (Table 5). |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Nexperia |
| Package | TSSOP-14 |
| Category | Logic ICs |
| Pins | 14 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage (absolute maximum) | VCC | -0.5 | | 7 | V | | 3 |
| Input voltage (absolute maximum) | VI | -0.5 | | 7 | V | | 3 |
| Input clamping current | IIK | -20 | | | mA | VI < -0.5 V | 3 |
| Output clamping current | IOK | -20 | | 20 | mA | VO < -0.5 V or VO > VCC + 0.5 V | 3 |
| Output current | IO | -25 | | 25 | mA | VO = -0.5 V to (VCC + 0.5 V) | 3 |
| Supply current | ICC | | | 75 | mA | | 3 |
| Ground current | IGND | -75 | | | mA | | 3 |
| Storage temperature | Tstg | -65 | | 150 | °C | | 3 |
| Total power dissipation | Ptot | | | 500 | mW | Tamb = -40 °C to +125 °C; SOT402-1 (TSSOP14) derates 7.3 mW/K above 81 °C | 3 |
| Supply voltage (recommended) | VCC | 2 | 5 | 5.5 | V | | 4 |
| Input voltage (recommended) | VI | 0 | | 5.5 | V | | 4 |
| Output voltage (recommended) | VO | 0 | | | V | | 4 |
| Ambient temperature | Tamb | -40 | 25 | 125 | °C | | 4 |
| Input transition rise and fall rate | Δt/ΔV | | | 100 | ns/V | VCC = 3.0 V to 3.6 V | 4 |
| Input transition rise and fall rate | Δt/ΔV | | | 20 | ns/V | VCC = 4.5 V to 5.5 V | 4 |
| HIGH-level input voltage | VIH | 1.5 | | | V | VCC = 2.0 V; 25 °C | 4 |
| HIGH-level input voltage | VIH | 2.1 | | | V | VCC = 3.0 V; 25 °C | 4 |
| HIGH-level input voltage | VIH | 3.85 | | | V | VCC = 5.5 V; 25 °C | 4 |
| LOW-level input voltage | VIL | | | 0.5 | V | VCC = 2.0 V; 25 °C | 4 |
| LOW-level input voltage | VIL | | | 0.9 | V | VCC = 3.0 V; 25 °C | 4 |
| LOW-level input voltage | VIL | | | 1.65 | V | VCC = 5.5 V; 25 °C | 4 |
| HIGH-level output voltage | VOH | 1.9 | 2 | | V | VI = VIH or VIL; IO = -50 μA; VCC = 2.0 V; 25 °C | 4 |
| HIGH-level output voltage | VOH | 1.9 | | | V | VI = VIH or VIL; IO = -50 μA; VCC = 2.0 V; -40 °C to +125 °C | 4 |
| HIGH-level output voltage | VOH | 2.9 | 3 | | V | VI = VIH or VIL; IO = -50 μA; VCC = 3.0 V; 25 °C | 4 |
| HIGH-level output voltage | VOH | 2.9 | | | V | VI = VIH or VIL; IO = -50 μA; VCC = 3.0 V; -40 °C to +125 °C | 4 |
| HIGH-level output voltage | VOH | 4.4 | 4.5 | | V | VI = VIH or VIL; IO = -50 μA; VCC = 4.5 V; 25 °C | 4 |
| HIGH-level output voltage | VOH | 4.4 | | | V | VI = VIH or VIL; IO = -50 μA; VCC = 4.5 V; -40 °C to +125 °C | 4 |
| HIGH-level output voltage | VOH | 2.58 | | | V | VI = VIH or VIL; IO = -4.0 mA; VCC = 3.0 V; 25 °C | 4 |
| HIGH-level output voltage | VOH | 2.4 | | | V | VI = VIH or VIL; IO = -4.0 mA; VCC = 3.0 V; -40 °C to +125 °C | 4 |
| HIGH-level output voltage | VOH | 3.94 | | | V | VI = VIH or VIL; IO = -8.0 mA; VCC = 4.5 V; 25 °C | 4 |
| HIGH-level output voltage | VOH | 3.7 | | | V | VI = VIH or VIL; IO = -8.0 mA; VCC = 4.5 V; -40 °C to +125 °C | 4 |
| LOW-level output voltage | VOL | | 0 | 0.1 | V | VI = VIH or VIL; IO = 50 μA; VCC = 2.0 V; 25 °C | 4 |
| LOW-level output voltage | VOL | | | 0.1 | V | VI = VIH or VIL; IO = 50 μA; VCC = 2.0 V; -40 °C to +125 °C | 4 |
| LOW-level output voltage | VOL | | | 0.36 | V | VI = VIH or VIL; IO = 4.0 mA; VCC = 3.0 V; 25 °C | 4 |
| LOW-level output voltage | VOL | | | 0.55 | V | VI = VIH or VIL; IO = 4.0 mA; VCC = 3.0 V; -40 °C to +125 °C | 4 |
| Input leakage current | II | | | 0.1 | μA | VI = 5.5 V or GND; VCC = 0 V to 5.5 V; 25 °C | 4 |
| Input leakage current | II | | | 2 | μA | VI = 5.5 V or GND; VCC = 0 V to 5.5 V; -40 °C to +125 °C | 4 |
| Supply current | ICC | | | 2 | μA | VI = VCC or GND; IO = 0 A; VCC = 5.5 V; 25 °C | 4 |
| Supply current | ICC | | | 40 | μA | VI = VCC or GND; IO = 0 A; VCC = 5.5 V; -40 °C to +125 °C | 4 |
| Input capacitance | CI | | 3 | 10 | pF | VI = VCC or GND; 25 °C | 4 |
| Propagation delay | tpd | | 3.9 | 7.9 | ns | nA, nB to nY; VCC = 3.0 V to 3.6 V; CL = 15 pF; 25 °C | 5 |
| Propagation delay | tpd | 1 | | 10 | ns | nA, nB to nY; VCC = 3.0 V to 3.6 V; CL = 15 pF; -40 °C to +125 °C | 5 |
| Propagation delay | tpd | | 5.6 | 11.4 | ns | nA, nB to nY; VCC = 3.0 V to 3.6 V; CL = 50 pF; 25 °C | 5 |
| Propagation delay | tpd | 1 | | 14.5 | ns | nA, nB to nY; VCC = 3.0 V to 3.6 V; CL = 50 pF; -40 °C to +125 °C | 5 |
| Propagation delay | tpd | | 2.8 | 5.5 | ns | nA, nB to nY; VCC = 4.5 V to 5.5 V; CL = 15 pF; 25 °C | 5 |
| Propagation delay | tpd | 1 | | 7 | ns | nA, nB to nY; VCC = 4.5 V to 5.5 V; CL = 15 pF; -40 °C to +125 °C | 5 |
| Propagation delay | tpd | | 4.1 | 7.5 | ns | nA, nB to nY; VCC = 4.5 V to 5.5 V; CL = 50 pF; 25 °C | 5 |
| Propagation delay | tpd | 1 | | 9.5 | ns | nA, nB to nY; VCC = 4.5 V to 5.5 V; CL = 50 pF; -40 °C to +125 °C | 5 |
## CAD (KiCad official)
- Symbol: `74AHC32PW`
- Footprint: `Package_SO:TSSOP-14_4.4x5mm_P0.65mm`
- 3D model: TSSOP-14 (KiCad packages3D, STEP)
- 3D model files: `74ahc32pw-etched.step` / `74ahc32pw-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `74ahc32pw.step` / `74ahc32pw.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Nexperia datasheet](https://assets.nexperia.com/documents/data-sheet/74AHC_AHCT32.pdf) (13 pp, sha256 `71f897a7a0bfa4c3`, retrieved 2026-10-28, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/74ahc32pw-datasheet.pdf)