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74AHC32PW-Q100J
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Nexperia Logic Gates, TSSOP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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74AHC32PW-Q100J
Nexperia · Logic Gates · TSSOP-14
74AHC32PW-Q100J from Nexperia, in a TSSOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1A | input | Data input 1A of OR gate 1; inputs are overvoltage tolerant to 5.5 V and have Schmitt-trigger action. |
| 2 | 1B | input | Data input 1B of OR gate 1; inputs are overvoltage tolerant to 5.5 V and have Schmitt-trigger action. |
| 3 | 1Y | output | Data output 1Y of OR gate 1, where 1Y = 1A OR 1B. |
| 4 | 2A | input | Data input 2A of OR gate 2; inputs are overvoltage tolerant to 5.5 V and have Schmitt-trigger action. |
| 5 | 2B | input | Data input 2B of OR gate 2; inputs are overvoltage tolerant to 5.5 V and have Schmitt-trigger action. |
| 6 | 2Y | output | Data output 2Y of OR gate 2, where 2Y = 2A OR 2B. |
| 7 | GND | power_in | Ground (0 V) reference for all voltages; the datasheet specifies 0 V. |
| 8 | 3Y | output | Data output 3Y of OR gate 3, where 3Y = 3A OR 3B. |
| 9 | 3A | input | Data input 3A of OR gate 3; inputs are overvoltage tolerant to 5.5 V and have Schmitt-trigger action. |
| 10 | 3B | input | Data input 3B of OR gate 3; inputs are overvoltage tolerant to 5.5 V and have Schmitt-trigger action. |
| 11 | 4Y | output | Data output 4Y of OR gate 4, where 4Y = 4A OR 4B. |
| 12 | 4A | input | Data input 4A of OR gate 4; inputs are overvoltage tolerant to 5.5 V and have Schmitt-trigger action. |
| 13 | 4B | input | Data input 4B of OR gate 4; inputs are overvoltage tolerant to 5.5 V and have Schmitt-trigger action. |
| 14 | VCC | power_in | Supply voltage: 2.0 V to 5.5 V for 74AHC32-Q100 and 4.5 V to 5.5 V for 74AHCT32-Q100 (absolute maximum 7.0 V). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Nexperia |
| Package | TSSOP-14 |
| Category | Logic |
| Pins | 14 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VCC supply voltage | VCC | 2 | 5 | 5.5 | V | 4 | |
| input voltage | VI | 0 | 5.5 | V | 4 | ||
| output voltage | VO | 0 | V | 4 | |||
| ambient temperature | Tamb | -40 | 25 | 125 | °C | 4 | |
| input transition rise and fall rate | Δt/ΔV | 100 | ns/V | VCC = 3.0 V to 3.6 V | 4 | ||
| input transition rise and fall rate | Δt/ΔV | 20 | ns/V | VCC = 4.5 V to 5.5 V | 4 | ||
| supply voltage | VCC | -0.5 | 7 | V | 3 | ||
| input voltage | VI | -0.5 | 7 | V | 3 | ||
| input clamping current | IIK | -20 | mA | VI < -0.5 V | 3 | ||
| output clamping current | IOK | -20 | 20 | mA | VO < -0.5 V or VO > VCC + 0.5 V | 3 | |
| output current | IO | -25 | 25 | mA | VO = -0.5 V to (VCC + 0.5 V) | 3 | |
| supply current | ICC | 75 | mA | 3 | |||
| ground current | IGND | -75 | mA | 3 | |||
| storage temperature | Tstg | -65 | 150 | °C | 3 | ||
| total power dissipation | Ptot | 500 | mW | Tamb = -40 °C to +125 °C | 3 | ||
| HIGH-level input voltage | VIH | 1.5 | V | VCC = 2.0 V; 25 °C | 4 | ||
| HIGH-level input voltage | VIH | 2.1 | V | VCC = 3.0 V; 25 °C | 4 | ||
| HIGH-level input voltage | VIH | 3.85 | V | VCC = 5.5 V; 25 °C | 4 | ||
| LOW-level input voltage | VIL | 0.5 | V | VCC = 2.0 V; 25 °C | 4 | ||
| LOW-level input voltage | VIL | 0.9 | V | VCC = 3.0 V; 25 °C | 4 | ||
| LOW-level input voltage | VIL | 1.65 | V | VCC = 5.5 V; 25 °C | 4 | ||
| HIGH-level output voltage | VOH | 1.9 | 2 | V | VI = VIH or VIL; IO = -50 μA; VCC = 2.0 V; 25 °C | 4 | |
| HIGH-level output voltage | VOH | 1.9 | V | VI = VIH or VIL; IO = -50 μA; VCC = 2.0 V; -40 °C to +125 °C | 4 | ||
| HIGH-level output voltage | VOH | 2.9 | 3 | V | VI = VIH or VIL; IO = -50 μA; VCC = 3.0 V; 25 °C | 4 | |
| HIGH-level output voltage | VOH | 2.9 | V | VI = VIH or VIL; IO = -50 μA; VCC = 3.0 V; -40 °C to +125 °C | 4 | ||
| HIGH-level output voltage | VOH | 4.4 | 4.5 | V | VI = VIH or VIL; IO = -50 μA; VCC = 4.5 V; 25 °C | 4 | |
| HIGH-level output voltage | VOH | 4.4 | V | VI = VIH or VIL; IO = -50 μA; VCC = 4.5 V; -40 °C to +125 °C | 4 | ||
| HIGH-level output voltage | VOH | 2.58 | V | VI = VIH or VIL; IO = -4.0 mA; VCC = 3.0 V; 25 °C | 4 | ||
| HIGH-level output voltage | VOH | 2.4 | V | VI = VIH or VIL; IO = -4.0 mA; VCC = 3.0 V; -40 °C to +125 °C | 4 | ||
| HIGH-level output voltage | VOH | 3.94 | V | VI = VIH or VIL; IO = -8.0 mA; VCC = 4.5 V; 25 °C | 4 | ||
| HIGH-level output voltage | VOH | 3.7 | V | VI = VIH or VIL; IO = -8.0 mA; VCC = 4.5 V; -40 °C to +125 °C | 4 | ||
| LOW-level output voltage | VOL | 0 | 0.1 | V | VI = VIH or VIL; IO = 50 μA; VCC = 2.0 V; 25 °C | 4 | |
| LOW-level output voltage | VOL | 0.1 | V | VI = VIH or VIL; IO = 50 μA; VCC = 2.0 V; -40 °C to +125 °C | 4 | ||
| LOW-level output voltage | VOL | 0.36 | V | VI = VIH or VIL; IO = 4.0 mA; VCC = 3.0 V; 25 °C | 4 | ||
| LOW-level output voltage | VOL | 0.55 | V | VI = VIH or VIL; IO = 4.0 mA; VCC = 3.0 V; -40 °C to +125 °C | 4 | ||
| input leakage current | II | 0.1 | μA | VI = 5.5 V or GND; VCC = 0 V to 5.5 V; 25 °C | 4 | ||
| input leakage current | II | 2 | μA | VI = 5.5 V or GND; VCC = 0 V to 5.5 V; -40 °C to +125 °C | 4 | ||
| supply current | ICC | 2 | μA | VI = VCC or GND; IO = 0 A; VCC = 5.5 V; 25 °C | 4 | ||
| supply current | ICC | 40 | μA | VI = VCC or GND; IO = 0 A; VCC = 5.5 V; -40 °C to +125 °C | 4 | ||
| input capacitance | CI | 10 | pF | VI = VCC or GND; -40 °C to +125 °C | 4 | ||
| propagation delay nA, nB to nY | tpd | 3.9 | 7.9 | ns | VCC = 3.0 V to 3.6 V; CL = 15 pF; 25 °C | 5 | |
| propagation delay nA, nB to nY | tpd | 1 | 10 | ns | VCC = 3.0 V to 3.6 V; CL = 15 pF; -40 °C to +125 °C | 5 | |
| propagation delay nA, nB to nY | tpd | 5.6 | 11.4 | ns | VCC = 3.0 V to 3.6 V; CL = 50 pF; 25 °C | 5 | |
| propagation delay nA, nB to nY | tpd | 1 | 14.5 | ns | VCC = 3.0 V to 3.6 V; CL = 50 pF; -40 °C to +125 °C | 5 | |
| propagation delay nA, nB to nY | tpd | 2.8 | 5.5 | ns | VCC = 4.5 V to 5.5 V; CL = 15 pF; 25 °C | 5 | |
| propagation delay nA, nB to nY | tpd | 1 | 7 | ns | VCC = 4.5 V to 5.5 V; CL = 15 pF; -40 °C to +125 °C | 5 | |
| propagation delay nA, nB to nY | tpd | 4.1 | 7.5 | ns | VCC = 4.5 V to 5.5 V; CL = 50 pF; 25 °C | 5 | |
| propagation delay nA, nB to nY | tpd | 1 | 9.5 | ns | VCC = 4.5 V to 5.5 V; CL = 50 pF; -40 °C to +125 °C | 5 |
CAD (KiCad official)
- Symbol:
74AHC32PW-Q100J - Footprint:
Package_SO:TSSOP-14_4.4x5mm_P0.65mm - 3D model: TSSOP-14 (KiCad packages3D, STEP)
- 3D model files:
74ahc32pw-q100j-etched.step/74ahc32pw-q100j-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);74ahc32pw-q100j.step/74ahc32pw-q100j.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Nexperia datasheet (13 pp, sha256
584eb7f5ed99cfbb, retrieved 2026-10-18, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# 74AHC32PW-Q100J
**Nexperia** · Logic Gates · TSSOP-14
74AHC32PW-Q100J from Nexperia, in a TSSOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1A | input | Data input 1A of OR gate 1; inputs are overvoltage tolerant to 5.5 V and have Schmitt-trigger action. |
| 2 | 1B | input | Data input 1B of OR gate 1; inputs are overvoltage tolerant to 5.5 V and have Schmitt-trigger action. |
| 3 | 1Y | output | Data output 1Y of OR gate 1, where 1Y = 1A OR 1B. |
| 4 | 2A | input | Data input 2A of OR gate 2; inputs are overvoltage tolerant to 5.5 V and have Schmitt-trigger action. |
| 5 | 2B | input | Data input 2B of OR gate 2; inputs are overvoltage tolerant to 5.5 V and have Schmitt-trigger action. |
| 6 | 2Y | output | Data output 2Y of OR gate 2, where 2Y = 2A OR 2B. |
| 7 | GND | power_in | Ground (0 V) reference for all voltages; the datasheet specifies 0 V. |
| 8 | 3Y | output | Data output 3Y of OR gate 3, where 3Y = 3A OR 3B. |
| 9 | 3A | input | Data input 3A of OR gate 3; inputs are overvoltage tolerant to 5.5 V and have Schmitt-trigger action. |
| 10 | 3B | input | Data input 3B of OR gate 3; inputs are overvoltage tolerant to 5.5 V and have Schmitt-trigger action. |
| 11 | 4Y | output | Data output 4Y of OR gate 4, where 4Y = 4A OR 4B. |
| 12 | 4A | input | Data input 4A of OR gate 4; inputs are overvoltage tolerant to 5.5 V and have Schmitt-trigger action. |
| 13 | 4B | input | Data input 4B of OR gate 4; inputs are overvoltage tolerant to 5.5 V and have Schmitt-trigger action. |
| 14 | VCC | power_in | Supply voltage: 2.0 V to 5.5 V for 74AHC32-Q100 and 4.5 V to 5.5 V for 74AHCT32-Q100 (absolute maximum 7.0 V). |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Nexperia |
| Package | TSSOP-14 |
| Category | Logic |
| Pins | 14 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VCC supply voltage | VCC | 2 | 5 | 5.5 | V | | 4 |
| input voltage | VI | 0 | | 5.5 | V | | 4 |
| output voltage | VO | 0 | | | V | | 4 |
| ambient temperature | Tamb | -40 | 25 | 125 | °C | | 4 |
| input transition rise and fall rate | Δt/ΔV | | | 100 | ns/V | VCC = 3.0 V to 3.6 V | 4 |
| input transition rise and fall rate | Δt/ΔV | | | 20 | ns/V | VCC = 4.5 V to 5.5 V | 4 |
| supply voltage | VCC | -0.5 | | 7 | V | | 3 |
| input voltage | VI | -0.5 | | 7 | V | | 3 |
| input clamping current | IIK | -20 | | | mA | VI < -0.5 V | 3 |
| output clamping current | IOK | -20 | | 20 | mA | VO < -0.5 V or VO > VCC + 0.5 V | 3 |
| output current | IO | -25 | | 25 | mA | VO = -0.5 V to (VCC + 0.5 V) | 3 |
| supply current | ICC | | | 75 | mA | | 3 |
| ground current | IGND | -75 | | | mA | | 3 |
| storage temperature | Tstg | -65 | | 150 | °C | | 3 |
| total power dissipation | Ptot | | | 500 | mW | Tamb = -40 °C to +125 °C | 3 |
| HIGH-level input voltage | VIH | 1.5 | | | V | VCC = 2.0 V; 25 °C | 4 |
| HIGH-level input voltage | VIH | 2.1 | | | V | VCC = 3.0 V; 25 °C | 4 |
| HIGH-level input voltage | VIH | 3.85 | | | V | VCC = 5.5 V; 25 °C | 4 |
| LOW-level input voltage | VIL | | | 0.5 | V | VCC = 2.0 V; 25 °C | 4 |
| LOW-level input voltage | VIL | | | 0.9 | V | VCC = 3.0 V; 25 °C | 4 |
| LOW-level input voltage | VIL | | | 1.65 | V | VCC = 5.5 V; 25 °C | 4 |
| HIGH-level output voltage | VOH | 1.9 | 2 | | V | VI = VIH or VIL; IO = -50 μA; VCC = 2.0 V; 25 °C | 4 |
| HIGH-level output voltage | VOH | 1.9 | | | V | VI = VIH or VIL; IO = -50 μA; VCC = 2.0 V; -40 °C to +125 °C | 4 |
| HIGH-level output voltage | VOH | 2.9 | 3 | | V | VI = VIH or VIL; IO = -50 μA; VCC = 3.0 V; 25 °C | 4 |
| HIGH-level output voltage | VOH | 2.9 | | | V | VI = VIH or VIL; IO = -50 μA; VCC = 3.0 V; -40 °C to +125 °C | 4 |
| HIGH-level output voltage | VOH | 4.4 | 4.5 | | V | VI = VIH or VIL; IO = -50 μA; VCC = 4.5 V; 25 °C | 4 |
| HIGH-level output voltage | VOH | 4.4 | | | V | VI = VIH or VIL; IO = -50 μA; VCC = 4.5 V; -40 °C to +125 °C | 4 |
| HIGH-level output voltage | VOH | 2.58 | | | V | VI = VIH or VIL; IO = -4.0 mA; VCC = 3.0 V; 25 °C | 4 |
| HIGH-level output voltage | VOH | 2.4 | | | V | VI = VIH or VIL; IO = -4.0 mA; VCC = 3.0 V; -40 °C to +125 °C | 4 |
| HIGH-level output voltage | VOH | 3.94 | | | V | VI = VIH or VIL; IO = -8.0 mA; VCC = 4.5 V; 25 °C | 4 |
| HIGH-level output voltage | VOH | 3.7 | | | V | VI = VIH or VIL; IO = -8.0 mA; VCC = 4.5 V; -40 °C to +125 °C | 4 |
| LOW-level output voltage | VOL | | 0 | 0.1 | V | VI = VIH or VIL; IO = 50 μA; VCC = 2.0 V; 25 °C | 4 |
| LOW-level output voltage | VOL | | | 0.1 | V | VI = VIH or VIL; IO = 50 μA; VCC = 2.0 V; -40 °C to +125 °C | 4 |
| LOW-level output voltage | VOL | | | 0.36 | V | VI = VIH or VIL; IO = 4.0 mA; VCC = 3.0 V; 25 °C | 4 |
| LOW-level output voltage | VOL | | | 0.55 | V | VI = VIH or VIL; IO = 4.0 mA; VCC = 3.0 V; -40 °C to +125 °C | 4 |
| input leakage current | II | | | 0.1 | μA | VI = 5.5 V or GND; VCC = 0 V to 5.5 V; 25 °C | 4 |
| input leakage current | II | | | 2 | μA | VI = 5.5 V or GND; VCC = 0 V to 5.5 V; -40 °C to +125 °C | 4 |
| supply current | ICC | | | 2 | μA | VI = VCC or GND; IO = 0 A; VCC = 5.5 V; 25 °C | 4 |
| supply current | ICC | | | 40 | μA | VI = VCC or GND; IO = 0 A; VCC = 5.5 V; -40 °C to +125 °C | 4 |
| input capacitance | CI | | | 10 | pF | VI = VCC or GND; -40 °C to +125 °C | 4 |
| propagation delay nA, nB to nY | tpd | | 3.9 | 7.9 | ns | VCC = 3.0 V to 3.6 V; CL = 15 pF; 25 °C | 5 |
| propagation delay nA, nB to nY | tpd | 1 | | 10 | ns | VCC = 3.0 V to 3.6 V; CL = 15 pF; -40 °C to +125 °C | 5 |
| propagation delay nA, nB to nY | tpd | | 5.6 | 11.4 | ns | VCC = 3.0 V to 3.6 V; CL = 50 pF; 25 °C | 5 |
| propagation delay nA, nB to nY | tpd | 1 | | 14.5 | ns | VCC = 3.0 V to 3.6 V; CL = 50 pF; -40 °C to +125 °C | 5 |
| propagation delay nA, nB to nY | tpd | | 2.8 | 5.5 | ns | VCC = 4.5 V to 5.5 V; CL = 15 pF; 25 °C | 5 |
| propagation delay nA, nB to nY | tpd | 1 | | 7 | ns | VCC = 4.5 V to 5.5 V; CL = 15 pF; -40 °C to +125 °C | 5 |
| propagation delay nA, nB to nY | tpd | | 4.1 | 7.5 | ns | VCC = 4.5 V to 5.5 V; CL = 50 pF; 25 °C | 5 |
| propagation delay nA, nB to nY | tpd | 1 | | 9.5 | ns | VCC = 4.5 V to 5.5 V; CL = 50 pF; -40 °C to +125 °C | 5 |
## CAD (KiCad official)
- Symbol: `74AHC32PW-Q100J`
- Footprint: `Package_SO:TSSOP-14_4.4x5mm_P0.65mm`
- 3D model: TSSOP-14 (KiCad packages3D, STEP)
- 3D model files: `74ahc32pw-q100j-etched.step` / `74ahc32pw-q100j-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `74ahc32pw-q100j.step` / `74ahc32pw-q100j.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Nexperia datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588908397282668544) (13 pp, sha256 `584eb7f5ed99cfbb`, retrieved 2026-10-18, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/74ahc32pw-q100j-datasheet.pdf)