main
History Download
Ray Publish 0.1.0 8e63e33 5d ago

74AHC244BQ

Nexperia · Buffers, Drivers, Receivers, Transceivers · DHVQFN-20-EP(2.5x4.5)

74AHC244BQ from Nexperia, in a DHVQFN-20-EP(2.5x4.5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 1OE input Active-LOW output enable for outputs 1Y0 to 1Y3; a HIGH level forces these outputs to the high-impedance OFF-state.
2 1A0 input Data input 1A0 of the first 4-bit buffer section.
3 2Y0 tri_state 3-state data output 2Y0 of the second 4-bit buffer section; high-impedance when 2OE is HIGH.
4 1A1 input Data input 1A1 of the first 4-bit buffer section.
5 2Y1 tri_state 3-state data output 2Y1 of the second 4-bit buffer section; high-impedance when 2OE is HIGH.
6 1A2 input Data input 1A2 of the first 4-bit buffer section.
7 2Y2 tri_state 3-state data output 2Y2 of the second 4-bit buffer section; high-impedance when 2OE is HIGH.
8 1A3 input Data input 1A3 of the first 4-bit buffer section.
9 2Y3 tri_state 3-state data output 2Y3 of the second 4-bit buffer section; high-impedance when 2OE is HIGH.
10 GND power_in Ground (0 V); all voltages are referenced to this pin.
11 2A3 input Data input 2A3 of the second 4-bit buffer section.
12 1Y3 tri_state 3-state data output 1Y3 of the first 4-bit buffer section; high-impedance when 1OE is HIGH.
13 2A2 input Data input 2A2 of the second 4-bit buffer section.
14 1Y2 tri_state 3-state data output 1Y2 of the first 4-bit buffer section; high-impedance when 1OE is HIGH.
15 2A1 input Data input 2A1 of the second 4-bit buffer section.
16 1Y1 tri_state 3-state data output 1Y1 of the first 4-bit buffer section; high-impedance when 1OE is HIGH.
17 2A0 input Data input 2A0 of the second 4-bit buffer section.
18 1Y0 tri_state 3-state data output 1Y0 of the first 4-bit buffer section; high-impedance when 1OE is HIGH.
19 2OE input Active-LOW output enable for outputs 2Y0 to 2Y3; a HIGH level forces these outputs to the high-impedance OFF-state.
20 VCC power_in Supply voltage; recommended 2.0 V to 5.5 V for 74AHC244 and 4.5 V to 5.5 V for 74AHCT244, with absolute maximum -0.5 V to +7.0 V.
21 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Nexperia
Package DHVQFN-20-EP(2.5x4.5)
Category Logic
Pins 21

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
supply voltage VCC 2 5 5.5 V 4
input voltage VI 0 5.5 V 4
output voltage VO 0 V 4
ambient temperature Tamb -40 25 125 °C 4
input transition rise and fall rate Δt/ΔV 100 ns/V VCC = 3.3 V ± 0.3 V 4
input transition rise and fall rate Δt/ΔV 20 ns/V VCC = 5.0 V ± 0.5 V 4
supply voltage VCC -0.5 7 V 4
input voltage VI -0.5 7 V 4
input clamping current IIK -20 mA VI < -0.5 V 4
output clamping current IOK -20 20 mA VO < -0.5 V or VO > VCC + 0.5 V 4
output current IO -25 25 mA VO = -0.5 V to VCC + 0.5 V 4
supply current ICC 75 mA 4
ground current IGND -75 mA 4
storage temperature Tstg -65 150 °C 4
total power dissipation Ptot 500 mW Tamb = -40 °C to +125 °C 4
propagation delay nAn to nYn tpd 5 8.4 ns VCC = 3.0 V to 3.6 V; CL = 15 pF; 25 °C 7
propagation delay nAn to nYn tpd 7 11.9 ns VCC = 3.0 V to 3.6 V; CL = 50 pF; 25 °C 7
propagation delay nAn to nYn tpd 3.4 5.5 ns VCC = 4.5 V to 5.5 V; CL = 15 pF; 25 °C 7
propagation delay nAn to nYn tpd 5 7.5 ns VCC = 4.5 V to 5.5 V; CL = 50 pF; 25 °C 7
enable time nOE to nYn ten 6.5 10.6 ns VCC = 3.0 V to 3.6 V; CL = 15 pF; see Fig. 5; 25 °C 7
enable time nOE to nYn ten 7.5 14.1 ns VCC = 3.0 V to 3.6 V; CL = 50 pF; see Fig. 5; 25 °C 7
enable time nOE to nYn ten 4 7.3 ns VCC = 4.5 V to 5.5 V; CL = 15 pF; see Fig. 5; 25 °C 7
enable time nOE to nYn ten 5.5 9.3 ns VCC = 4.5 V to 5.5 V; CL = 50 pF; see Fig. 5; 25 °C 7
disable time nOE to nYn tdis 5.5 9.7 ns VCC = 3.0 V to 3.6 V; CL = 15 pF; see Fig. 5; 25 °C 7
disable time nOE to nYn tdis 10 14 ns VCC = 3.0 V to 3.6 V; CL = 50 pF; see Fig. 5; 25 °C 7
disable time nOE to nYn tdis 4.8 7.2 ns VCC = 4.5 V to 5.5 V; CL = 15 pF; see Fig. 5; 25 °C 7
disable time nOE to nYn tdis 7 9.2 ns VCC = 4.5 V to 5.5 V; CL = 50 pF; see Fig. 5; 25 °C 7
propagation delay nAn to nYn tpd 1 10.5 ns VCC = 3.0 V to 3.6 V; CL = 15 pF; -40 °C to +125 °C 7
propagation delay nAn to nYn tpd 1 15 ns VCC = 3.0 V to 3.6 V; CL = 50 pF; -40 °C to +125 °C 7
propagation delay nAn to nYn tpd 1 7 ns VCC = 4.5 V to 5.5 V; CL = 15 pF; -40 °C to +125 °C 7
propagation delay nAn to nYn tpd 1 9.5 ns VCC = 4.5 V to 5.5 V; CL = 50 pF; -40 °C to +125 °C 7
enable time nOE to nYn ten 1 13.5 ns VCC = 3.0 V to 3.6 V; CL = 15 pF; see Fig. 5; -40 °C to +125 °C 7
enable time nOE to nYn ten 1 18 ns VCC = 3.0 V to 3.6 V; CL = 50 pF; see Fig. 5; -40 °C to +125 °C 7
enable time nOE to nYn ten 1 9.5 ns VCC = 4.5 V to 5.5 V; CL = 15 pF; see Fig. 5; -40 °C to +125 °C 7
enable time nOE to nYn ten 1 12 ns VCC = 4.5 V to 5.5 V; CL = 50 pF; see Fig. 5; -40 °C to +125 °C 7
disable time nOE to nYn tdis 1 12.5 ns VCC = 3.0 V to 3.6 V; CL = 15 pF; see Fig. 5; -40 °C to +125 °C 7
disable time nOE to nYn tdis 1 17.5 ns VCC = 3.0 V to 3.6 V; CL = 50 pF; see Fig. 5; -40 °C to +125 °C 7
disable time nOE to nYn tdis 1 9 ns VCC = 4.5 V to 5.5 V; CL = 15 pF; see Fig. 5; -40 °C to +125 °C 7
disable time nOE to nYn tdis 1 11.5 ns VCC = 4.5 V to 5.5 V; CL = 50 pF; see Fig. 5; -40 °C to +125 °C 7
HIGH-level input voltage VIH 1.5 V VCC = 2.0 V; -40 °C to +125 °C 5
HIGH-level input voltage VIH 2.1 V VCC = 3.0 V; -40 °C to +125 °C 5
HIGH-level input voltage VIH 3.85 V VCC = 5.5 V; -40 °C to +125 °C 5
LOW-level input voltage VIL 0.5 V VCC = 2.0 V; -40 °C to +125 °C 5
LOW-level input voltage VIL 0.9 V VCC = 3.0 V; -40 °C to +125 °C 5
LOW-level input voltage VIL 1.65 V VCC = 5.5 V; -40 °C to +125 °C 5
HIGH-level output voltage VOH 1.9 V VI = VIH or VIL; IO = -50 μA; VCC = 2.0 V; -40 °C to +125 °C 5
HIGH-level output voltage VOH 2.9 V VI = VIH or VIL; IO = -50 μA; VCC = 3.0 V; -40 °C to +125 °C 5
HIGH-level output voltage VOH 4.4 V VI = VIH or VIL; IO = -50 μA; VCC = 4.5 V; -40 °C to +125 °C 5
HIGH-level output voltage VOH 2.4 V VI = VIH or VIL; IO = -4.0 mA; VCC = 3.0 V; -40 °C to +125 °C 5
HIGH-level output voltage VOH 3.7 V VI = VIH or VIL; IO = -8.0 mA; VCC = 4.5 V; -40 °C to +125 °C 5
LOW-level output voltage VOL 0.1 V VI = VIH or VIL; IO = 50 μA; VCC = 2.0 V; -40 °C to +125 °C 5
LOW-level output voltage VOL 0.55 V VI = VIH or VIL; IO = 4.0 mA; VCC = 3.0 V; -40 °C to +125 °C 5
OFF-state output current IOZ -10 10 μA VI = VIH or VIL; VO = VCC or GND; VCC = 5.5 V; -40 °C to +125 °C 5
input leakage current II 2 μA VI = 5.5 V or GND; VCC = 0 V to 5.5 V; -40 °C to +125 °C 5
supply current ICC 80 μA VI = VCC or GND; IO = 0 A; VCC = 5.5 V; -40 °C to +125 °C 5
input capacitance CI 10 pF -40 °C to +125 °C 5

CAD (KiCad official)

  • Symbol: 74AHC244BQ
  • Footprint: Package_DFN_QFN:DHVQFN-20-1EP_2.5x4.5mm_P0.5mm_EP1x3mm
  • 3D model: DHVQFN-20-EP(2.5x4.5), generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 0.9 mm nominal VQFN height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
  • 3D model files: 74ahc244bq-etched.step / 74ahc244bq-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); 74ahc244bq.step / 74ahc244bq.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Nexperia datasheet (16 pp, sha256 88158be09d84b926, retrieved 2026-10-18, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF