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74AHC1G02GW

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Nexperia Logic Gates, SOT-353-5. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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74AHC1G02GW

Nexperia · Logic Gates · SOT-353-5

74AHC1G02GW from Nexperia, in a SOT-353-5. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 B input Data input B of the 2-input NOR gate, which is overvoltage tolerant up to 5.5 V.
2 A input Data input A of the 2-input NOR gate, which is overvoltage tolerant up to 5.5 V.
3 GND power_in Ground (0 V) reference for all voltages on the device.
4 Y output Data output Y of the NOR function, which gives Y = H only when both A and B are L.
5 VCC power_in Supply voltage, specified from 2.0 V to 5.5 V for 74AHC1G02 and 4.5 V to 5.5 V for 74AHCT1G02.

Key specifications

Parameter Value
Manufacturer Nexperia
Package SOT-353-5
Category Logic
Pins 5

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
VCC supply voltage VCC 2 5 5.5 V 3
input voltage VI 0 5.5 V 3
output voltage VO 0 V 3
ambient temperature Tamb -40 25 125 °C 3
input transition rise and fall rate Δt/ΔV 100 ns/V VCC = 3.3 V ± 0.3 V 3
input transition rise and fall rate Δt/ΔV 20 ns/V VCC = 5.0 V ± 0.5 V 3
supply voltage VCC -0.5 7 V 3
input voltage VI -0.5 7 V 3
input clamping current IIK -20 mA VI < -0.5 V 3
output clamping current IOK -20 20 mA VO < -0.5 V or VO > VCC + 0.5 V 3
output current IO -25 25 mA -0.5 V < VO < VCC + 0.5 V 3
supply current ICC 75 mA 3
ground current IGND -75 mA 3
storage temperature Tstg -65 150 °C 3
total power dissipation Ptot 250 mW Tamb = -40 °C to +125 °C 3
HIGH-level input voltage VIH 1.5 V VCC = 2.0 V; min over -40 °C to +125 °C 4
HIGH-level input voltage VIH 2.1 V VCC = 3.0 V; min over -40 °C to +125 °C 4
HIGH-level input voltage VIH 3.85 V VCC = 5.5 V; min over -40 °C to +125 °C 4
LOW-level input voltage VIL 0.5 V VCC = 2.0 V; max over -40 °C to +125 °C 4
LOW-level input voltage VIL 0.9 V VCC = 3.0 V; max over -40 °C to +125 °C 4
LOW-level input voltage VIL 1.65 V VCC = 5.5 V; max over -40 °C to +125 °C 4
HIGH-level output voltage VOH 1.9 2 V VI = VIH or VIL; IO = -50 μA; VCC = 2.0 V; min over -40 °C to +125 °C 4
HIGH-level output voltage VOH 2.9 3 V VI = VIH or VIL; IO = -50 μA; VCC = 3.0 V; min over -40 °C to +125 °C 4
HIGH-level output voltage VOH 4.4 4.5 V VI = VIH or VIL; IO = -50 μA; VCC = 4.5 V; min over -40 °C to +125 °C 4
HIGH-level output voltage VOH 2.4 V VI = VIH or VIL; IO = -4.0 mA; VCC = 3.0 V; min over -40 °C to +125 °C 4
HIGH-level output voltage VOH 3.7 V VI = VIH or VIL; IO = -8.0 mA; VCC = 4.5 V; min over -40 °C to +125 °C 4
LOW-level output voltage VOL 0 0.1 V VI = VIH or VIL; IO = 50 μA; VCC = 2.0 V; max over -40 °C to +125 °C 4
LOW-level output voltage VOL 0.55 V VI = VIH or VIL; IO = 4.0 mA; VCC = 3.0 V; max over -40 °C to +125 °C 4
input leakage current II 2 μA VI = 5.5 V or GND; VCC = 0 V to 5.5 V; max over -40 °C to +125 °C 4
supply current ICC 40 μA VI = VCC or GND; IO = 0 A; VCC = 5.5 V; max over -40 °C to +125 °C 4
input capacitance CI 1.5 10 pF 4
propagation delay tpd 1 4.4 10.5 ns A and B to Y; see Fig. 4; VCC = 3.0 V to 3.6 V; CL = 15 pF; min/max over -40 °C to +125 °C 5
propagation delay tpd 1 6.3 14.5 ns A and B to Y; see Fig. 4; VCC = 3.0 V to 3.6 V; CL = 50 pF; min/max over -40 °C to +125 °C 5
propagation delay tpd 1 3.2 7 ns A and B to Y; see Fig. 4; VCC = 4.5 V to 5.5 V; CL = 15 pF; min/max over -40 °C to +125 °C 5
propagation delay tpd 1 4.6 9.5 ns A and B to Y; see Fig. 4; VCC = 4.5 V to 5.5 V; CL = 50 pF; min/max over -40 °C to +125 °C 5

CAD (KiCad official)

  • Symbol: 74AHC1G02GW
  • Footprint: Package_TO_SOT_SMD:SOT-353_SC-70-5
  • 3D model: SOT-353-5 (KiCad packages3D, STEP)
  • 3D model files: 74ahc1g02gw-etched.step / 74ahc1g02gw-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); 74ahc1g02gw.step / 74ahc1g02gw.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Nexperia datasheet (11 pp, sha256 1b8adc489eaf14f8, retrieved 2026-10-17, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF