component
74AHC02D
Public Made by Adomby adom
Nexperia Logic Gates, SO-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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74AHC02D
Nexperia · Logic Gates · SO-14
74AHC02D from Nexperia, in a SO-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1Y | output | Data output 1Y of the first NOR gate, which goes HIGH only when both inputs 1A and 1B are LOW (Table 3). |
| 2 | 1A | input | Data input 1A of the first NOR gate; the datasheet specifies CMOS input levels for 74AHC02 and TTL input levels for 74AHCT02. |
| 3 | 1B | input | Data input 1B of the first NOR gate; inputs have Schmitt-trigger action and accept voltages higher than VCC (Section 2). |
| 4 | 2Y | output | Data output 2Y of the second NOR gate, which goes HIGH only when both inputs 2A and 2B are LOW (Table 3). |
| 5 | 2A | input | Data input 2A of the second NOR gate; the datasheet specifies CMOS input levels for 74AHC02 and TTL input levels for 74AHCT02. |
| 6 | 2B | input | Data input 2B of the second NOR gate; inputs have Schmitt-trigger action and accept voltages higher than VCC (Section 2). |
| 7 | GND | power_in | Ground pin at 0 V, to which all voltages in the datasheet are referenced. |
| 8 | 3A | input | Data input 3A of the third NOR gate; the datasheet specifies CMOS input levels for 74AHC02 and TTL input levels for 74AHCT02. |
| 9 | 3B | input | Data input 3B of the third NOR gate; inputs have Schmitt-trigger action and accept voltages higher than VCC (Section 2). |
| 10 | 3Y | output | Data output 3Y of the third NOR gate, which goes HIGH only when both inputs 3A and 3B are LOW (Table 3). |
| 11 | 4A | input | Data input 4A of the fourth NOR gate; the datasheet specifies CMOS input levels for 74AHC02 and TTL input levels for 74AHCT02. |
| 12 | 4B | input | Data input 4B of the fourth NOR gate; inputs have Schmitt-trigger action and accept voltages higher than VCC (Section 2). |
| 13 | 4Y | output | Data output 4Y of the fourth NOR gate, which goes HIGH only when both inputs 4A and 4B are LOW (Table 3). |
| 14 | VCC | power_in | Supply voltage; recommended range is 2.0 V to 5.5 V for 74AHC02 and 4.5 V to 5.5 V for 74AHCT02 (Table 5). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Nexperia |
| Package | SO-14 |
| Category | Logic |
| Pins | 14 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage | VCC | -0.5 | 7 | V | 3 | ||
| Input voltage | VI | -0.5 | 7 | V | 3 | ||
| Input clamping current | IIK | -20 | mA | VI < -0.5 V | 3 | ||
| Output clamping current | IOK | -20 | 20 | mA | VO < -0.5 V or VO > VCC + 0.5 V | 3 | |
| Output current | IO | -25 | 25 | mA | VO = -0.5 V to (VCC + 0.5 V) | 3 | |
| Supply current | ICC | 75 | mA | 3 | |||
| Ground current | IGND | -75 | mA | 3 | |||
| Storage temperature | Tstg | -65 | 150 | °C | 3 | ||
| Total power dissipation | Ptot | 500 | mW | Tamb = -40 °C to +125 °C | 3 | ||
| Supply voltage (74AHC02) | VCC | 2 | 5 | 5.5 | V | 3 | |
| Input voltage | VI | 0 | 5.5 | V | 3 | ||
| Output voltage | VO | 0 | V | VO max printed as VCC | 3 | ||
| Ambient temperature | Tamb | -40 | 25 | 125 | °C | 3 | |
| Input transition rise and fall rate | Δt/ΔV | 100 | ns/V | VCC = 3.0 V to 3.6 V | 3 | ||
| Input transition rise and fall rate | Δt/ΔV | 20 | ns/V | VCC = 4.5 V to 5.5 V | 3 | ||
| HIGH-level input voltage | VIH | 1.5 | V | VCC = 2.0 V | 4 | ||
| HIGH-level input voltage | VIH | 2.1 | V | VCC = 3.0 V | 4 | ||
| HIGH-level input voltage | VIH | 3.85 | V | VCC = 5.5 V | 4 | ||
| LOW-level input voltage | VIL | 0.5 | V | VCC = 2.0 V | 4 | ||
| LOW-level input voltage | VIL | 0.9 | V | VCC = 3.0 V | 4 | ||
| LOW-level input voltage | VIL | 1.65 | V | VCC = 5.5 V | 4 | ||
| HIGH-level output voltage | VOH | 1.9 | 2 | V | 25 °C; VI = VIH or VIL; IO = -50 μA; VCC = 2.0 V | 4 | |
| HIGH-level output voltage | VOH | 2.9 | 3 | V | 25 °C; VI = VIH or VIL; IO = -50 μA; VCC = 3.0 V | 4 | |
| HIGH-level output voltage | VOH | 4.4 | 4.5 | V | 25 °C; VI = VIH or VIL; IO = -50 μA; VCC = 4.5 V | 4 | |
| HIGH-level output voltage | VOH | 2.58 | V | 25 °C; VI = VIH or VIL; IO = -4.0 mA; VCC = 3.0 V | 4 | ||
| HIGH-level output voltage | VOH | 2.4 | V | -40 °C to +125 °C; VI = VIH or VIL; IO = -4.0 mA; VCC = 3.0 V | 4 | ||
| HIGH-level output voltage | VOH | 3.94 | V | 25 °C; VI = VIH or VIL; IO = -8.0 mA; VCC = 4.5 V | 4 | ||
| HIGH-level output voltage | VOH | 3.7 | V | -40 °C to +125 °C; VI = VIH or VIL; IO = -8.0 mA; VCC = 4.5 V | 4 | ||
| LOW-level output voltage | VOL | 0 | 0.1 | V | 25 °C; VI = VIH or VIL; IO = 50 μA; VCC = 2.0 V | 4 | |
| LOW-level output voltage | VOL | 0.36 | V | 25 °C; VI = VIH or VIL; IO = 4.0 mA; VCC = 3.0 V | 4 | ||
| LOW-level output voltage | VOL | 0.55 | V | -40 °C to +125 °C; VI = VIH or VIL; IO = 4.0 mA; VCC = 3.0 V | 4 | ||
| Input leakage current | II | 0.1 | μA | 25 °C; VI = 5.5 V or GND; VCC = 0 V to 5.5 V | 4 | ||
| Input leakage current | II | 2 | μA | -40 °C to +125 °C; VI = 5.5 V or GND; VCC = 0 V to 5.5 V | 4 | ||
| Supply current | ICC | 2 | μA | 25 °C; VI = VCC or GND; IO = 0 A; VCC = 5.5 V | 4 | ||
| Supply current | ICC | 40 | μA | -40 °C to +125 °C; VI = VCC or GND; IO = 0 A; VCC = 5.5 V | 4 | ||
| Input capacitance | CI | 3 | 10 | pF | 25 °C | 4 | |
| Propagation delay | tpd | 3.9 | 7.9 | ns | 25 °C; nA, nB to nY; VCC = 3.0 V to 3.6 V; CL = 15 pF | 5 | |
| Propagation delay | tpd | 1 | 10 | ns | -40 °C to +125 °C; nA, nB to nY; VCC = 3.0 V to 3.6 V; CL = 15 pF | 5 | |
| Propagation delay | tpd | 5.5 | 11.4 | ns | 25 °C; nA, nB to nY; VCC = 3.0 V to 3.6 V; CL = 50 pF | 5 | |
| Propagation delay | tpd | 1 | 14.5 | ns | -40 °C to +125 °C; nA, nB to nY; VCC = 3.0 V to 3.6 V; CL = 50 pF | 5 | |
| Propagation delay | tpd | 2.9 | 5.5 | ns | 25 °C; nA, nB to nY; VCC = 4.5 V to 5.5 V; CL = 15 pF | 5 | |
| Propagation delay | tpd | 1 | 7 | ns | -40 °C to +125 °C; nA, nB to nY; VCC = 4.5 V to 5.5 V; CL = 15 pF | 5 | |
| Propagation delay | tpd | 4.2 | 7.5 | ns | 25 °C; nA, nB to nY; VCC = 4.5 V to 5.5 V; CL = 50 pF | 5 | |
| Propagation delay | tpd | 1 | 9.5 | ns | -40 °C to +125 °C; nA, nB to nY; VCC = 4.5 V to 5.5 V; CL = 50 pF | 5 | |
| Power dissipation capacitance | CPD | 7 | pF | CL = 50 pF; fi = 1 MHz; VI = GND to VCC | 5 |
CAD (KiCad official)
- Symbol:
74AHC02D - Footprint:
Package_SO:SO-14_3.9x8.65mm_P1.27mm - 3D model: SO-14 (KiCad packages3D, STEP)
- 3D model files:
74ahc02d-etched.step/74ahc02d-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);74ahc02d.step/74ahc02d.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Nexperia datasheet (12 pp, sha256
c0f66f44ba5d162c, retrieved 2026-10-29, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# 74AHC02D
**Nexperia** · Logic Gates · SO-14
74AHC02D from Nexperia, in a SO-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1Y | output | Data output 1Y of the first NOR gate, which goes HIGH only when both inputs 1A and 1B are LOW (Table 3). |
| 2 | 1A | input | Data input 1A of the first NOR gate; the datasheet specifies CMOS input levels for 74AHC02 and TTL input levels for 74AHCT02. |
| 3 | 1B | input | Data input 1B of the first NOR gate; inputs have Schmitt-trigger action and accept voltages higher than VCC (Section 2). |
| 4 | 2Y | output | Data output 2Y of the second NOR gate, which goes HIGH only when both inputs 2A and 2B are LOW (Table 3). |
| 5 | 2A | input | Data input 2A of the second NOR gate; the datasheet specifies CMOS input levels for 74AHC02 and TTL input levels for 74AHCT02. |
| 6 | 2B | input | Data input 2B of the second NOR gate; inputs have Schmitt-trigger action and accept voltages higher than VCC (Section 2). |
| 7 | GND | power_in | Ground pin at 0 V, to which all voltages in the datasheet are referenced. |
| 8 | 3A | input | Data input 3A of the third NOR gate; the datasheet specifies CMOS input levels for 74AHC02 and TTL input levels for 74AHCT02. |
| 9 | 3B | input | Data input 3B of the third NOR gate; inputs have Schmitt-trigger action and accept voltages higher than VCC (Section 2). |
| 10 | 3Y | output | Data output 3Y of the third NOR gate, which goes HIGH only when both inputs 3A and 3B are LOW (Table 3). |
| 11 | 4A | input | Data input 4A of the fourth NOR gate; the datasheet specifies CMOS input levels for 74AHC02 and TTL input levels for 74AHCT02. |
| 12 | 4B | input | Data input 4B of the fourth NOR gate; inputs have Schmitt-trigger action and accept voltages higher than VCC (Section 2). |
| 13 | 4Y | output | Data output 4Y of the fourth NOR gate, which goes HIGH only when both inputs 4A and 4B are LOW (Table 3). |
| 14 | VCC | power_in | Supply voltage; recommended range is 2.0 V to 5.5 V for 74AHC02 and 4.5 V to 5.5 V for 74AHCT02 (Table 5). |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Nexperia |
| Package | SO-14 |
| Category | Logic |
| Pins | 14 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage | VCC | -0.5 | | 7 | V | | 3 |
| Input voltage | VI | -0.5 | | 7 | V | | 3 |
| Input clamping current | IIK | -20 | | | mA | VI < -0.5 V | 3 |
| Output clamping current | IOK | -20 | | 20 | mA | VO < -0.5 V or VO > VCC + 0.5 V | 3 |
| Output current | IO | -25 | | 25 | mA | VO = -0.5 V to (VCC + 0.5 V) | 3 |
| Supply current | ICC | | | 75 | mA | | 3 |
| Ground current | IGND | -75 | | | mA | | 3 |
| Storage temperature | Tstg | -65 | | 150 | °C | | 3 |
| Total power dissipation | Ptot | | | 500 | mW | Tamb = -40 °C to +125 °C | 3 |
| Supply voltage (74AHC02) | VCC | 2 | 5 | 5.5 | V | | 3 |
| Input voltage | VI | 0 | | 5.5 | V | | 3 |
| Output voltage | VO | 0 | | | V | VO max printed as VCC | 3 |
| Ambient temperature | Tamb | -40 | 25 | 125 | °C | | 3 |
| Input transition rise and fall rate | Δt/ΔV | | | 100 | ns/V | VCC = 3.0 V to 3.6 V | 3 |
| Input transition rise and fall rate | Δt/ΔV | | | 20 | ns/V | VCC = 4.5 V to 5.5 V | 3 |
| HIGH-level input voltage | VIH | 1.5 | | | V | VCC = 2.0 V | 4 |
| HIGH-level input voltage | VIH | 2.1 | | | V | VCC = 3.0 V | 4 |
| HIGH-level input voltage | VIH | 3.85 | | | V | VCC = 5.5 V | 4 |
| LOW-level input voltage | VIL | | | 0.5 | V | VCC = 2.0 V | 4 |
| LOW-level input voltage | VIL | | | 0.9 | V | VCC = 3.0 V | 4 |
| LOW-level input voltage | VIL | | | 1.65 | V | VCC = 5.5 V | 4 |
| HIGH-level output voltage | VOH | 1.9 | 2 | | V | 25 °C; VI = VIH or VIL; IO = -50 μA; VCC = 2.0 V | 4 |
| HIGH-level output voltage | VOH | 2.9 | 3 | | V | 25 °C; VI = VIH or VIL; IO = -50 μA; VCC = 3.0 V | 4 |
| HIGH-level output voltage | VOH | 4.4 | 4.5 | | V | 25 °C; VI = VIH or VIL; IO = -50 μA; VCC = 4.5 V | 4 |
| HIGH-level output voltage | VOH | 2.58 | | | V | 25 °C; VI = VIH or VIL; IO = -4.0 mA; VCC = 3.0 V | 4 |
| HIGH-level output voltage | VOH | 2.4 | | | V | -40 °C to +125 °C; VI = VIH or VIL; IO = -4.0 mA; VCC = 3.0 V | 4 |
| HIGH-level output voltage | VOH | 3.94 | | | V | 25 °C; VI = VIH or VIL; IO = -8.0 mA; VCC = 4.5 V | 4 |
| HIGH-level output voltage | VOH | 3.7 | | | V | -40 °C to +125 °C; VI = VIH or VIL; IO = -8.0 mA; VCC = 4.5 V | 4 |
| LOW-level output voltage | VOL | | 0 | 0.1 | V | 25 °C; VI = VIH or VIL; IO = 50 μA; VCC = 2.0 V | 4 |
| LOW-level output voltage | VOL | | | 0.36 | V | 25 °C; VI = VIH or VIL; IO = 4.0 mA; VCC = 3.0 V | 4 |
| LOW-level output voltage | VOL | | | 0.55 | V | -40 °C to +125 °C; VI = VIH or VIL; IO = 4.0 mA; VCC = 3.0 V | 4 |
| Input leakage current | II | | | 0.1 | μA | 25 °C; VI = 5.5 V or GND; VCC = 0 V to 5.5 V | 4 |
| Input leakage current | II | | | 2 | μA | -40 °C to +125 °C; VI = 5.5 V or GND; VCC = 0 V to 5.5 V | 4 |
| Supply current | ICC | | | 2 | μA | 25 °C; VI = VCC or GND; IO = 0 A; VCC = 5.5 V | 4 |
| Supply current | ICC | | | 40 | μA | -40 °C to +125 °C; VI = VCC or GND; IO = 0 A; VCC = 5.5 V | 4 |
| Input capacitance | CI | | 3 | 10 | pF | 25 °C | 4 |
| Propagation delay | tpd | | 3.9 | 7.9 | ns | 25 °C; nA, nB to nY; VCC = 3.0 V to 3.6 V; CL = 15 pF | 5 |
| Propagation delay | tpd | 1 | | 10 | ns | -40 °C to +125 °C; nA, nB to nY; VCC = 3.0 V to 3.6 V; CL = 15 pF | 5 |
| Propagation delay | tpd | | 5.5 | 11.4 | ns | 25 °C; nA, nB to nY; VCC = 3.0 V to 3.6 V; CL = 50 pF | 5 |
| Propagation delay | tpd | 1 | | 14.5 | ns | -40 °C to +125 °C; nA, nB to nY; VCC = 3.0 V to 3.6 V; CL = 50 pF | 5 |
| Propagation delay | tpd | | 2.9 | 5.5 | ns | 25 °C; nA, nB to nY; VCC = 4.5 V to 5.5 V; CL = 15 pF | 5 |
| Propagation delay | tpd | 1 | | 7 | ns | -40 °C to +125 °C; nA, nB to nY; VCC = 4.5 V to 5.5 V; CL = 15 pF | 5 |
| Propagation delay | tpd | | 4.2 | 7.5 | ns | 25 °C; nA, nB to nY; VCC = 4.5 V to 5.5 V; CL = 50 pF | 5 |
| Propagation delay | tpd | 1 | | 9.5 | ns | -40 °C to +125 °C; nA, nB to nY; VCC = 4.5 V to 5.5 V; CL = 50 pF | 5 |
| Power dissipation capacitance | CPD | | 7 | | pF | CL = 50 pF; fi = 1 MHz; VI = GND to VCC | 5 |
## CAD (KiCad official)
- Symbol: `74AHC02D`
- Footprint: `Package_SO:SO-14_3.9x8.65mm_P1.27mm`
- 3D model: SO-14 (KiCad packages3D, STEP)
- 3D model files: `74ahc02d-etched.step` / `74ahc02d-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `74ahc02d.step` / `74ahc02d.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Nexperia datasheet](https://assets.nexperia.com/documents/data-sheet/74AHC02D.pdf) (12 pp, sha256 `c0f66f44ba5d162c`, retrieved 2026-10-29, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/74ahc02d-datasheet.pdf)