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74ACT240MTC

Public Made by Adom

by adom

onsemi Buffers, Drivers, Receivers, Transceivers, TSSOP-20. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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74ACT240MTC

onsemi · Buffers, Drivers, Receivers, Transceivers · TSSOP-20

74ACT240MTC from onsemi, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 OE1 input Active-LOW 3-STATE output enable for outputs O0-O3; when HIGH, those outputs go to high impedance (Z).
2 I0 input Buffer data input for channel 0; ACT240 inputs are TTL-compatible and the input voltage range is 0V to VCC.
3 O4 tri_state Inverting 3-STATE output of channel 4, controlled by OE2; sources/sinks 24mA.
4 I1 input Buffer data input for channel 1; ACT240 inputs are TTL-compatible and the input voltage range is 0V to VCC.
5 O5 tri_state Inverting 3-STATE output of channel 5, controlled by OE2; sources/sinks 24mA.
6 I2 input Buffer data input for channel 2; ACT240 inputs are TTL-compatible and the input voltage range is 0V to VCC.
7 O6 tri_state Inverting 3-STATE output of channel 6, controlled by OE2; sources/sinks 24mA.
8 I3 input Buffer data input for channel 3; ACT240 inputs are TTL-compatible and the input voltage range is 0V to VCC.
9 O7 tri_state Inverting 3-STATE output of channel 7, controlled by OE2; sources/sinks 24mA.
10 GND power_in Ground reference for the device.
11 I7 input Buffer data input for channel 7; ACT240 inputs are TTL-compatible and the input voltage range is 0V to VCC.
12 O3 tri_state Inverting 3-STATE output of channel 3, controlled by OE1; sources/sinks 24mA.
13 I6 input Buffer data input for channel 6; ACT240 inputs are TTL-compatible and the input voltage range is 0V to VCC.
14 O2 tri_state Inverting 3-STATE output of channel 2, controlled by OE1; sources/sinks 24mA.
15 I5 input Buffer data input for channel 5; ACT240 inputs are TTL-compatible and the input voltage range is 0V to VCC.
16 O1 tri_state Inverting 3-STATE output of channel 1, controlled by OE1; sources/sinks 24mA.
17 I4 input Buffer data input for channel 4; ACT240 inputs are TTL-compatible and the input voltage range is 0V to VCC.
18 O0 tri_state Inverting 3-STATE output of channel 0, controlled by OE1; sources/sinks 24mA.
19 OE2 input Active-LOW 3-STATE output enable for outputs O4-O7; when HIGH, those outputs go to high impedance (Z).
20 VCC power_in Supply voltage: 74ACT240 is specified at 4.5V to 5.5V (absolute maximum −0.5V to +7.0V).

Key specifications

Parameter Value
Manufacturer onsemi
Package TSSOP-20
Category Logic
Pins 20

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Minimum HIGH Level Input Voltage (ACT) VIH 2 1.5 V VCC=4.5V; VOUT=0.1V or VCC − 0.1V; TA=-40°C to +85°C (typ at +25°C) 6
Maximum LOW Level Input Voltage (ACT) VIL 1.5 0.8 V VCC=4.5V; VOUT=0.1V or VCC − 0.1V; TA=-40°C to +85°C (typ at +25°C) 6
Minimum HIGH Level Output Voltage VOH 4.4 4.49 V VCC=4.5V; IOUT=−50µA; TA=-40°C to +85°C 6
Minimum HIGH Level Output Voltage VOH 4.4 5.49 V VCC=5.5V; IOUT=−50µA; TA=-40°C to +85°C 6
Minimum HIGH Level Output Voltage VOH 3.76 V VCC=4.5V; VIN=VIL or VIH, IOH=−24mA; TA=-40°C to +85°C (25°C limit 3.86) 6
Minimum HIGH Level Output Voltage VOH 4.76 V VCC=5.5V; VIN=VIL or VIH, IOH=−24mA(4); TA=-40°C to +85°C (25°C limit 4.86) 6
Maximum LOW Level Output Voltage VOL 0.001 0.1 V VCC=4.5V; IOUT=50µA; TA=-40°C to +85°C 6
Maximum LOW Level Output Voltage VOL 0.36 0.44 V VCC=4.5V; VIN=VIL or VIH, IOL=24mA; TA=-40°C to +85°C 6
Maximum Input Leakage Current IIN -1 0.1 1 µA VCC=5.5V; VI = VCC, GND 6
Maximum 3-STATE Leakage Current IOZ -2.5 0.25 2.5 µA VCC=5.5V; VI = VIL, VIH; VO = VCC, GND 6
Maximum ICC/Input ICCT 0.6 1.5 mA VCC=5.5V; VI = VCC − 2.1V 6
Minimum Dynamic Output Current IOLD 75 mA VCC=5.5V; VOLD = 1.65V Max. 6
Minimum Dynamic Output Current IOHD -75 mA VCC=5.5V; VOHD = 3.85V Min. 6
Maximum Quiescent Supply Current ICC 4 40 µA VCC=5.5V; VIN = VCC or GND 6
Propagation Delay Data to Output tPLH (5.0V ±0.5V) tPLH 1.5 6 8.5 ns VCC=5.0V; TA=+25°C, CL=50pF 7
Propagation Delay Data to Output tPLH (5.0V ±0.5V) tPLH 1.5 9.5 ns VCC=5.0V; TA=-40°C to +85°C, CL=50pF 7
Propagation Delay Data to Output tPHL (5.0V ±0.5V) tPHL 1.5 5.5 7.5 ns VCC=5.0V; TA=+25°C, CL=50pF 7
Propagation Delay Data to Output tPHL (5.0V ±0.5V) tPHL 1.5 8.5 ns VCC=5.0V; TA=-40°C to +85°C, CL=50pF 7
Output Enable Time tPZH (5.0V ±0.5V) tPZH 1.5 7 8.5 ns VCC=5.0V; TA=+25°C, CL=50pF 7
Output Enable Time tPZH (5.0V ±0.5V) tPZH 1 9.5 ns VCC=5.0V; TA=-40°C to +85°C, CL=50pF 7
Output Enable Time tPZL (5.0V ±0.5V) tPZL 2 7 9.5 ns VCC=5.0V; TA=+25°C, CL=50pF 7
Output Enable Time tPZL (5.0V ±0.5V) tPZL 1.5 10.5 ns VCC=5.0V; TA=-40°C to +85°C, CL=50pF 7
Output Disable Time tPHZ (5.0V ±0.5V) tPHZ 2 8 9.5 ns VCC=5.0V; TA=+25°C, CL=50pF 7
Output Disable Time tPHZ (5.0V ±0.5V) tPHZ 2 10.5 ns VCC=5.0V; TA=-40°C to +85°C, CL=50pF 7
Output Disable Time tPLZ (5.0V ±0.5V) tPLZ 2.5 6.5 10 ns VCC=5.0V; TA=+25°C, CL=50pF 7
Output Disable Time tPLZ (5.0V ±0.5V) tPLZ 2 10.5 ns VCC=5.0V; TA=-40°C to +85°C, CL=50pF 7
Supply Voltage (ACT) VCC 4.5 5.5 V ACT devices 4
Input Voltage VI 0 V Maximum printed as 0V to VCC 4
Output Voltage VO 0 V Maximum printed as 0V to VCC 4
Operating Temperature TA -40 85 °C 4
Minimum Input Edge Rate, ACT Devices ΔV / Δt 125 mV/ns VIN from 0.8V to 2.0V, VCC @ 4.5V, 5.5V 4
Supply Voltage VCC -0.5 7 V 4
DC Input Diode Current IIK -20 mA VI = −0.5V 4
DC Input Diode Current IIK 20 mA VI = VCC + 0.5 4
DC Input Voltage VI -0.5 V Maximum printed as VCC + 0.5V 4
DC Output Diode Current IOK -20 mA VO = −0.5V 4
DC Output Diode Current IOK 20 mA VO = VCC + 0.5V 4
DC Output Voltage VO -0.5 V Maximum printed as VCC + 0.5V 4
DC Output Source or Sink Current IO -50 50 mA 4
DC VCC or Ground Current per Output Pin ICC or IGND -50 50 mA 4
Storage Temperature TSTG -65 150 °C 4
Junction Temperature TJ 140 °C 4

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
housing PC 74AC240PC N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide 2

CAD (KiCad official)

  • Symbol: 74ACT240MTC
  • Footprint: Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm
  • 3D model: TSSOP-20 (KiCad packages3D, STEP)
  • 3D model files: 74act240mtc-etched.step / 74act240mtc-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); 74act240mtc.step / 74act240mtc.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: onsemi datasheet (13 pp, sha256 dca960fd9ff7c398, retrieved 2026-10-21, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF