# 74ACT11074DBR

**Texas Instruments** · Flip Flops · SSOP-14-208mil

74ACT11074DBR from Texas Instruments, in a SSOP-14-208mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1PRE | input | Active-low asynchronous preset for flip-flop 1; a low level sets 1Q high regardless of the other inputs. |
| 2 | 1Q | output | True output of flip-flop 1; recommended IOH is -24 mA and IOL is 24 mA. |
| 3 | 1Q̅ | output | Complementary output of flip-flop 1; recommended IOH is -24 mA and IOL is 24 mA. |
| 4 | GND | power_in | Ground reference; the center-pin VCC and GND configuration is used to minimize high-speed switching noise. |
| 5 | 2Q | output | True output of flip-flop 2; recommended IOH is -24 mA and IOL is 24 mA. |
| 6 | 2Q | output | Complementary output of flip-flop 2; recommended IOH is -24 mA and IOL is 24 mA. |
| 7 | 2PRE | input | Active-low asynchronous preset for flip-flop 2; a low level sets 2Q high regardless of the other inputs. |
| 8 | 2CLK | input | Positive-edge clock for flip-flop 2; maximum clock frequency is 100 MHz and data transfers on the low-to-high transition. |
| 9 | 2D | input | Data input for flip-flop 2; data must meet the 4.5 ns setup time before CLK rises and the 0 ns hold time after CLK rises. |
| 10 | 2CLR | input | Active-low asynchronous clear for flip-flop 2; a low level resets 2Q low regardless of the other inputs. |
| 11 | VCC | power_in | Supply voltage, recommended 4.5 V to 5.5 V (absolute maximum -0.5 V to 6 V); center-pin VCC configuration. |
| 12 | 1CLR | input | Active-low asynchronous clear for flip-flop 1; a low level resets 1Q low regardless of the other inputs. |
| 13 | 1D | input | Data input for flip-flop 1; data must meet the 4.5 ns setup time before CLK rises and the 0 ns hold time after CLK rises. |
| 14 | 1CLK | input | Positive-edge clock for flip-flop 1; maximum clock frequency is 100 MHz and data transfers on the low-to-high transition. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SSOP-14-208mil |
| Category | Logic |
| Pins | 14 |

## CAD (KiCad official)

- Symbol: `74ACT11074DBR`
- Footprint: `Package_SO:SSOP-14_5.3x6.2mm_P0.65mm`
- 3D model: SSOP-14-208mil (KiCad packages3D, STEP)
- 3D model files: `74act11074dbr-etched.step` / `74act11074dbr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `74act11074dbr.step` / `74act11074dbr.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/74act11074) (18 pp, sha256 `4945034b621283d1`, retrieved 2026-10-11, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/74act11074dbr-datasheet.pdf)