component
74ACT11030DR
Public Made by Adomby adom
Texas Instruments Logic Gates, SOIC-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
Open in new tab ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.
Symbol & Footprint
Schematic Symbol
Open full view ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
PCB Footprint
Open full view ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
Datasheet
Open in new tab ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
README
markdown74ACT11030DR
Texas Instruments · Logic Gates · SOIC-14
74ACT11030DR from Texas Instruments, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | C | input | Gate input C, TTL-compatible with VIH min 2 V and VIL max 0.8 V. |
| 2 | B | input | Gate input B, TTL-compatible with VIH min 2 V and VIL max 0.8 V. |
| 3 | A | input | Gate input A, TTL-compatible with VIH min 2 V and VIL max 0.8 V. |
| 4 | GND | power_in | Ground pin (center-pin GND configuration to minimize high-speed switching noise). |
| 5 | Y | output | NAND output, low only when all inputs A through H are high; rated for IOH of -24 mA and IOL of 24 mA. |
| 6 | NC | unconnected | No internal connection. |
| 7 | NC | unconnected | No internal connection. |
| 8 | H | input | Gate input H, TTL-compatible with VIH min 2 V and VIL max 0.8 V. |
| 9 | G | input | Gate input G, TTL-compatible with VIH min 2 V and VIL max 0.8 V. |
| 10 | NC | unconnected | No internal connection. |
| 11 | VCC | power_in | Supply voltage pin, recommended 4.5 V to 5.5 V (center-pin VCC configuration). |
| 12 | F | input | Gate input F, TTL-compatible with VIH min 2 V and VIL max 0.8 V. |
| 13 | E | input | Gate input E, TTL-compatible with VIH min 2 V and VIL max 0.8 V. |
| 14 | D | input | Gate input D, TTL-compatible with VIH min 2 V and VIL max 0.8 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOIC-14 |
| Category | Logic |
| Pins | 14 |
CAD (KiCad official)
- Symbol:
74ACT11030DR - Footprint:
Package_SO:SOIC-14_3.9x8.7mm_P1.27mm - 3D model: SOIC-14 (KiCad packages3D, STEP)
- 3D model files:
74act11030dr-etched.step/74act11030dr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);74act11030dr.step/74act11030dr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (13 pp, sha256
2fd133b559591a03, retrieved 2026-10-11, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).