74ACT11000DR

{
  "slug": "74act11000dr",
  "version": "0.1.0",
  "type": "component",
  "description": "Texas Instruments Logic Gates, SOIC-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
  "tags": [
    "component",
    "logic",
    "74act11000dr",
    "factory-2.0.0",
    "extractor-text"
  ],
  "dependencies": {},
  "hero": {
    "type": "image",
    "path": "docs/hero.png"
  },
  "files": [
    "page.json",
    "README.md",
    "74act11000dr.kicad_sym",
    "74act11000dr.kicad_mod",
    "74act11000dr.glb",
    "74act11000dr.step",
    "74act11000dr.lbr",
    "docs/hero.png",
    "docs/74act11000dr-datasheet.pdf",
    "viewers/symbol.html",
    "viewers/footprint.html",
    "74act11000dr-hero.glb",
    "74act11000dr-hero.overlay.json"
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  "component": {
    "mpn": "74ACT11000DR",
    "manufacturer": "Texas Instruments",
    "package": "SOIC-16",
    "pin_count": 16,
    "category": "Logic",
    "subcategory": "Logic Gates",
    "datasheet": "https://www.ti.com/lit/ds/symlink/74act11000.pdf",
    "parts": {
      "symbol": "74act11000dr.kicad_sym",
      "footprint": "74act11000dr.kicad_mod",
      "model_3d": "74act11000dr-hero.glb",
      "model_3d_plain": "74act11000dr.glb",
      "model_3d_step": "74act11000dr-etched.step",
      "model_3d_step_plain": "74act11000dr.step",
      "lbr": "74act11000dr.lbr"
    },
    "distributor_links": {
      "lcsc": "C2878029",
      "digikey": "296-14295-2-ND",
      "mouser": "595-74ACT11000DR"
    },
    "distributor_check": {
      "checked_at": "2026-10-08T17:58:13Z",
      "source": "Component Ocean /api/assign-pns",
      "digikey": {
        "pn": "296-14295-2-ND",
        "status": "found",
        "lifecycle": "Active"
      },
      "mouser": {
        "pn": "595-74ACT11000DR",
        "status": "found"
      }
    },
    "pins": [
      {
        "number": "1",
        "name": "1A",
        "type": "input",
        "description": "Input A of NAND gate 1; TTL-compatible, with VIH minimum 2 V, VIL maximum 0.8 V, and input range 0 V to VCC."
      },
      {
        "number": "2",
        "name": "1Y",
        "type": "output",
        "description": "Output of NAND gate 1, Y = A·B in positive logic; sources up to -24 mA (IOH) and sinks up to 24 mA (IOL)."
      },
      {
        "number": "3",
        "name": "2Y",
        "type": "output",
        "description": "Output of NAND gate 2, Y = A·B in positive logic; sources up to -24 mA (IOH) and sinks up to 24 mA (IOL)."
      },
      {
        "number": "4",
        "name": "GND",
        "type": "power_in",
        "description": "Ground reference for the device; one of two GND pins that should both be connected."
      },
      {
        "number": "5",
        "name": "GND",
        "type": "power_in",
        "description": "Ground reference for the device; one of two GND pins that should both be connected."
      },
      {
        "number": "6",
        "name": "3Y",
        "type": "output",
        "description": "Output of NAND gate 3, Y = A·B in positive logic; sources up to -24 mA (IOH) and sinks up to 24 mA (IOL)."
      },
      {
        "number": "7",
        "name": "4Y",
        "type": "output",
        "description": "Output of NAND gate 4, Y = A·B in positive logic; sources up to -24 mA (IOH) and sinks up to 24 mA (IOL)."
      },
      {
        "number": "8",
        "name": "4B",
        "type": "input",
        "description": "Input B of NAND gate 4; TTL-compatible, with VIH minimum 2 V, VIL maximum 0.8 V, and input range 0 V to VCC."
      },
      {
        "number": "9",
        "name": "4A",
        "type": "input",
        "description": "Input A of NAND gate 4; TTL-compatible, with VIH minimum 2 V, VIL maximum 0.8 V, and input range 0 V to VCC."
      },
      {
        "number": "10",
        "name": "3B",
        "type": "input",
        "description": "Input B of NAND gate 3; TTL-compatible, with VIH minimum 2 V, VIL maximum 0.8 V, and input range 0 V to VCC."
      },
      {
        "number": "11",
        "name": "3A",
        "type": "input",
        "description": "Input A of NAND gate 3; TTL-compatible, with VIH minimum 2 V, VIL maximum 0.8 V, and input range 0 V to VCC."
      },
      {
        "number": "12",
        "name": "VCC",
        "type": "power_in",
        "description": "Supply voltage, 4.5 V to 5.5 V recommended; one of two VCC pins that should both be connected."
      },
      {
        "number": "13",
        "name": "VCC",
        "type": "power_in",
        "description": "Supply voltage, 4.5 V to 5.5 V recommended; one of two VCC pins that should both be connected."
      },
      {
        "number": "14",
        "name": "2B",
        "type": "input",
        "description": "Input B of NAND gate 2; TTL-compatible, with VIH minimum 2 V, VIL maximum 0.8 V, and input range 0 V to VCC."
      },
      {
        "number": "15",
        "name": "2A",
        "type": "input",
        "description": "Input A of NAND gate 2; TTL-compatible, with VIH minimum 2 V, VIL maximum 0.8 V, and input range 0 V to VCC."
      },
      {
        "number": "16",
        "name": "1B",
        "type": "input",
        "description": "Input B of NAND gate 1; TTL-compatible, with VIH minimum 2 V, VIL maximum 0.8 V, and input range 0 V to VCC."
      }
    ],
    "provenance": {
      "extractor": "extract_pins 0.3",
      "factory_chain": {
        "factory": "2.0.0",
        "extractor": "extract_pins 0.3",
        "primary_model": "claude-haiku-5-5",
        "primary_mode": "text",
        "consensus_model": "claude-sonnet-5-5",
        "consensus": "agreed",
        "guards": "pin_guards 0.1: passed",
        "guard_notes": [
          "extractor flagged: The pin-to-name mapping was reconstructed from scrambled text extraction of the top-view diagram on ; The datasheet pin figure covers the D, J and N packages, and the pin numbers shown are for the D, J ; Pin descriptions are limited to what the datasheet states (logic function, recommended VCC of 4.5 to"
        ],
        "pages_sent": 10,
        "cost_usd": 0.0627,
        "at": "2026-10-08T17:57:34"
      },
      "datasheet": {
        "url": "https://www.ti.com/lit/ds/symlink/74act11000.pdf",
        "pages": 10,
        "sha256": "12ce66baa18c48d4",
        "source_tier": "mfr"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 16,
        "described": 16,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
    },
    "viewers": {
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      "footprint": "viewers/footprint.html"
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        "role": "plain",
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        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
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        "zmin_mm": -0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "d5eeddb4c0b304dc61950919b126fc61d7586abd5f16ab71a2a79759ec6498bf",
        "checked": "2026-10-08",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      },
      {
        "file": "74act11000dr-etched.step",
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        "checked": "2026-10-08",
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  }
}