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74act08mtc: factory component page (tier=lcsc)

Ray ·846235dc96 ·1mo ago ·parent 1c091fd
1 file changed +174−8
page.json+174−8
@@ -1,13 +1,184 @@ {+  "schema_version": 1,+  "type": "component",   "slug": "74act08mtc",+  "title": "74ACT08MTC",+  "brief": "onsemi Logic Gates, TSSOP-14. Datasheet-verified pinout, KiCad symbol/footprint/3D.",   "version": "0.1.0",-  "type": "component",-  "description": "onsemi Logic Gates, TSSOP-14. Datasheet-verified pinout, KiCad symbol/footprint/3D.",+  "license": "CC-BY-SA-4.0",   "tags": [     "component",     "logic",     "74act08mtc"   ],+  "component": {+    "mpn": "74ACT08MTC",+    "manufacturer": "onsemi",+    "package": "TSSOP-14",+    "pin_count": 14,+    "category": "Logic",+    "subcategory": "Logic Gates",+    "datasheet": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8589997703792271361",+    "parts": {+      "symbol": "74act08mtc.kicad_sym",+      "footprint": "74act08mtc.kicad_mod",+      "model_3d": "74act08mtc.glb",+      "model_3d_step": "74act08mtc.step",+      "lbr": "74act08mtc.lbr"+    },+    "distributor_links": {},+    "pins": [+      {+        "number": "1",+        "name": "A0",+        "type": "input",+        "description": "Input A of gate 0 (first 2-input AND gate). TTL-compatible input threshold (VIH min 2.0V, VIL max 0.8V at VCC=4.5-5.5V)."+      },+      {+        "number": "2",+        "name": "B0",+        "type": "input",+        "description": "Input B of gate 0 (first 2-input AND gate). TTL-compatible input threshold (VIH min 2.0V, VIL max 0.8V at VCC=4.5-5.5V)."+      },+      {+        "number": "3",+        "name": "O0",+        "type": "output",+        "description": "Output of gate 0 = A0 AND B0. Push-pull CMOS output sourcing/sinking 24 mA (VOH \u2265 3.76V @ IOH=-24mA, VOL \u2264 0.44V @ IOL=24mA at VCC=4.5V)."+      },+      {+        "number": "4",+        "name": "A1",+        "type": "input",+        "description": "Input A of gate 1 (second 2-input AND gate). TTL-compatible input threshold (VIH min 2.0V, VIL max 0.8V at VCC=4.5-5.5V)."+      },+      {+        "number": "5",+        "name": "B1",+        "type": "input",+        "description": "Input B of gate 1 (second 2-input AND gate). TTL-compatible input threshold (VIH min 2.0V, VIL max 0.8V at VCC=4.5-5.5V)."+      },+      {+        "number": "6",+        "name": "O1",+        "type": "output",+        "description": "Output of gate 1 = A1 AND B1. Push-pull CMOS output sourcing/sinking 24 mA (VOH \u2265 3.76V @ IOH=-24mA, VOL \u2264 0.44V @ IOL=24mA at VCC=4.5V)."+      },+      {+        "number": "7",+        "name": "GND",+        "type": "power_in",+        "description": "Ground reference (0V). Common ground return for all four gates."+      },+      {+        "number": "8",+        "name": "O3",+        "type": "output",+        "description": "Output of gate 3 = A3 AND B3. Push-pull CMOS output sourcing/sinking 24 mA (VOH \u2265 3.76V @ IOH=-24mA, VOL \u2264 0.44V @ IOL=24mA at VCC=4.5V)."+      },+      {+        "number": "9",+        "name": "B3",+        "type": "input",+        "description": "Input B of gate 3 (fourth 2-input AND gate). TTL-compatible input threshold (VIH min 2.0V, VIL max 0.8V at VCC=4.5-5.5V)."+      },+      {+        "number": "10",+        "name": "A3",+        "type": "input",+        "description": "Input A of gate 3 (fourth 2-input AND gate). TTL-compatible input threshold (VIH min 2.0V, VIL max 0.8V at VCC=4.5-5.5V)."+      },+      {+        "number": "11",+        "name": "O2",+        "type": "output",+        "description": "Output of gate 2 = A2 AND B2. Push-pull CMOS output sourcing/sinking 24 mA (VOH \u2265 3.76V @ IOH=-24mA, VOL \u2264 0.44V @ IOL=24mA at VCC=4.5V)."+      },+      {+        "number": "12",+        "name": "B2",+        "type": "input",+        "description": "Input B of gate 2 (third 2-input AND gate). TTL-compatible input threshold (VIH min 2.0V, VIL max 0.8V at VCC=4.5-5.5V)."+      },+      {+        "number": "13",+        "name": "A2",+        "type": "input",+        "description": "Input A of gate 2 (third 2-input AND gate). TTL-compatible input threshold (VIH min 2.0V, VIL max 0.8V at VCC=4.5-5.5V)."+      },+      {+        "number": "14",+        "name": "VCC",+        "type": "power_in",+        "description": "Positive supply voltage. Recommended operating range 4.5V to 5.5V for 74ACT08 (TTL-compatible thresholds). Absolute maximum -0.5V to +7.0V."+      }+    ],+    "provenance": {+      "extractor": "ds2sf",+      "datasheet": {+        "url": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8589997703792271361",+        "pages": 7,+        "sha256": "d37456fb09b16dc7",+        "source_tier": "lcsc"+      },+      "cad": "KiCad official (CC-BY-SA 4.0)",+      "pins": {+        "total": 14,+        "described": 14,+        "cites_pages": true,+        "refuses_to_fabricate": true+      }+    },+    "viewers": {+      "symbol": "viewers/symbol.html",+      "footprint": "viewers/footprint.html"+    }+  },+  "metadata": {+    "specs": {+      "Manufacturer": "onsemi",+      "Package": "TSSOP-14",+      "Category": "Logic",+      "Pins": "14"+    }+  },+  "variants": [+    {+      "mpn": "74ACT08MTC",+      "kind": "packaging"+    },+    {+      "mpn": "74ACT08MTCX",+      "kind": "packaging"+    },+    {+      "mpn": "74ACT08MTCSC",+      "kind": "packaging"+    },+    {+      "mpn": "74ACT08MTCSCX",+      "kind": "packaging"+    },+    {+      "mpn": "74ACT08MTCPC",+      "kind": "packaging"+    }+  ],+  "sections": [+    "hero",+    "viewers",+    "readme",+    "breadcrumbs",+    "info"+  ],+  "discovery_triggers": [+    "74act08mtc"+  ],+  "discovery_pitch": "74ACT08MTC (onsemi) component page with datasheet-verified CAD.",+  "author": {+    "name": "Ray",+    "email": "[email protected]"+  },   "dependencies": {},   "hero": {     "type": "image",@@ -25,10 +196,5 @@     "docs/74act08mtc-datasheet.pdf",     "viewers/symbol.html",     "viewers/footprint.html"-  ],-  "visibility": "public",-  "author": {-    "name": "Ray",-    "email": "[email protected]"-  }+  ] }\ No newline at end of file