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Initial commit: component/74ac11008pwr

Ray ·610aaaf0e5 ·15h ago
2 files changed +260
README.mdadded+52
@@ -0,0 +1,52 @@+# 74AC11008PWR++**Texas Instruments** · Logic Gates · TSSOP-16++74AC11008PWR from Texas Instruments, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | 1A | input | Gate 1 input A; Y = A·B, with VIH min 2.1 V at VCC = 3 V and 3.15 V at 4.5 V. |+| 2 | 1Y | output | Gate 1 output; rated for IOH of -24 mA and IOL of 24 mA at VCC = 4.5 V. |+| 3 | 2Y | output | Gate 2 output; rated for IOH of -24 mA and IOL of 24 mA at VCC = 4.5 V. |+| 4 | GND | power_in | Ground (center-pin GND configuration, tied with pin 5 to minimize switching noise). |+| 5 | GND | power_in | Ground (center-pin GND configuration, tied with pin 4 to minimize switching noise). |+| 6 | 3Y | output | Gate 3 output; rated for IOH of -24 mA and IOL of 24 mA at VCC = 4.5 V. |+| 7 | 4Y | output | Gate 4 output; rated for IOH of -24 mA and IOL of 24 mA at VCC = 4.5 V. |+| 8 | 4B | input | Gate 4 input B; Y = A·B, with VIL max 1.35 V at VCC = 4.5 V. |+| 9 | 4A | input | Gate 4 input A; Y = A·B, with input voltage range 0 V to VCC. |+| 10 | 3B | input | Gate 3 input B; Y = A·B, with input voltage range 0 V to VCC. |+| 11 | 3A | input | Gate 3 input A; Y = A·B, with input voltage range 0 V to VCC. |+| 12 | VCC | power_in | Supply voltage (center-pin VCC, tied with pin 13); recommended 3 V to 5.5 V, absolute maximum 7 V. |+| 13 | VCC | power_in | Supply voltage (center-pin VCC, tied with pin 12); recommended 3 V to 5.5 V, absolute maximum 7 V. |+| 14 | 2B | input | Gate 2 input B; Y = A·B, with input voltage range 0 V to VCC. |+| 15 | 2A | input | Gate 2 input A; Y = A·B, with input voltage range 0 V to VCC. |+| 16 | 1B | input | Gate 1 input B; Y = A·B, with input voltage range 0 V to VCC. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | TSSOP-16 |+| Category | Logic |+| Pins | 16 |++## CAD (KiCad official)++- Symbol: `74AC11008PWR`+- Footprint: `Package_SO:TSSOP-16_4.4x5mm_P0.65mm`+- 3D model: TSSOP-16 (KiCad packages3D, STEP)+- 3D model files: `74ac11008pwr-etched.step` / `74ac11008pwr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `74ac11008pwr.step` / `74ac11008pwr.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/lit/ds/symlink/74ac11008.pdf) (15 pp, sha256 `8f9e10b6605a144a`, retrieved 2026-10-06, tier: manufacturer)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-4-5-20251001` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/74ac11008pwr-datasheet.pdf)
page.jsonadded+208
@@ -0,0 +1,208 @@+{+  "slug": "74ac11008pwr",+  "version": "0.1.0",+  "type": "component",+  "description": "Texas Instruments Logic Gates, TSSOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+  "tags": [+    "component",+    "logic",+    "74ac11008pwr",+    "factory-2.0.0",+    "extractor-text"+  ],+  "dependencies": {},+  "hero": {+    "type": "image",+    "path": "docs/hero.png"+  },+  "files": [+    "page.json",+    "README.md",+    "74ac11008pwr.kicad_sym",+    "74ac11008pwr.kicad_mod",+    "74ac11008pwr.glb",+    "74ac11008pwr.step",+    "74ac11008pwr.lbr",+    "docs/hero.png",+    "docs/74ac11008pwr-datasheet.pdf",+    "viewers/symbol.html",+    "viewers/footprint.html",+    "74ac11008pwr-hero.glb",+    "74ac11008pwr-hero.overlay.json"+  ],+  "component": {+    "mpn": "74AC11008PWR",+    "manufacturer": "Texas Instruments",+    "package": "TSSOP-16",+    "pin_count": 16,+    "category": "Logic",+    "subcategory": "Logic Gates",+    "datasheet": "https://www.ti.com/lit/ds/symlink/74ac11008.pdf",+    "parts": {+      "symbol": "74ac11008pwr.kicad_sym",+      "footprint": "74ac11008pwr.kicad_mod",+      "model_3d": "74ac11008pwr-hero.glb",+      "model_3d_plain": "74ac11008pwr.glb",+      "model_3d_step": "74ac11008pwr-etched.step",+      "model_3d_step_plain": "74ac11008pwr.step",+      "lbr": "74ac11008pwr.lbr"+    },+    "distributor_links": {+      "lcsc": 2877028,+      "digikey": "296-4155-2-ND",+      "mouser": "595-74AC11008PWR"+    },+    "distributor_check": {+      "checked_at": "2026-10-06T17:22:06Z",+      "source": "Component Ocean /api/assign-pns",+      "digikey": {+        "pn": "296-4155-2-ND",+        "status": "found",+        "lifecycle": "Active"+      },+      "mouser": {+        "pn": "595-74AC11008PWR",+        "status": "found"+      }+    },+    "pins": [+      {+        "number": "1",+        "name": "1A",+        "type": "input",+        "description": "Gate 1 input A; Y = A·B, with VIH min 2.1 V at VCC = 3 V and 3.15 V at 4.5 V."+      },+      {+        "number": "2",+        "name": "1Y",+        "type": "output",+        "description": "Gate 1 output; rated for IOH of -24 mA and IOL of 24 mA at VCC = 4.5 V."+      },+      {+        "number": "3",+        "name": "2Y",+        "type": "output",+        "description": "Gate 2 output; rated for IOH of -24 mA and IOL of 24 mA at VCC = 4.5 V."+      },+      {+        "number": "4",+        "name": "GND",+        "type": "power_in",+        "description": "Ground (center-pin GND configuration, tied with pin 5 to minimize switching noise)."+      },+      {+        "number": "5",+        "name": "GND",+        "type": "power_in",+        "description": "Ground (center-pin GND configuration, tied with pin 4 to minimize switching noise)."+      },+      {+        "number": "6",+        "name": "3Y",+        "type": "output",+        "description": "Gate 3 output; rated for IOH of -24 mA and IOL of 24 mA at VCC = 4.5 V."+      },+      {+        "number": "7",+        "name": "4Y",+        "type": "output",+        "description": "Gate 4 output; rated for IOH of -24 mA and IOL of 24 mA at VCC = 4.5 V."+      },+      {+        "number": "8",+        "name": "4B",+        "type": "input",+        "description": "Gate 4 input B; Y = A·B, with VIL max 1.35 V at VCC = 4.5 V."+      },+      {+        "number": "9",+        "name": "4A",+        "type": "input",+        "description": "Gate 4 input A; Y = A·B, with input voltage range 0 V to VCC."+      },+      {+        "number": "10",+        "name": "3B",+        "type": "input",+        "description": "Gate 3 input B; Y = A·B, with input voltage range 0 V to VCC."+      },+      {+        "number": "11",+        "name": "3A",+        "type": "input",+        "description": "Gate 3 input A; Y = A·B, with input voltage range 0 V to VCC."+      },+      {+        "number": "12",+        "name": "VCC",+        "type": "power_in",+        "description": "Supply voltage (center-pin VCC, tied with pin 13); recommended 3 V to 5.5 V, absolute maximum 7 V."+      },+      {+        "number": "13",+        "name": "VCC",+        "type": "power_in",+        "description": "Supply voltage (center-pin VCC, tied with pin 12); recommended 3 V to 5.5 V, absolute maximum 7 V."+      },+      {+        "number": "14",+        "name": "2B",+        "type": "input",+        "description": "Gate 2 input B; Y = A·B, with input voltage range 0 V to VCC."+      },+      {+        "number": "15",+        "name": "2A",+        "type": "input",+        "description": "Gate 2 input A; Y = A·B, with input voltage range 0 V to VCC."+      },+      {+        "number": "16",+        "name": "1B",+        "type": "input",+        "description": "Gate 1 input B; Y = A·B, with input voltage range 0 V to VCC."+      }+    ],+    "provenance": {+      "extractor": "extract_pins 0.3",+      "factory_chain": {+        "factory": "2.0.0",+        "extractor": "extract_pins 0.3",+        "primary_model": "claude-haiku-4-5-20251001",+        "primary_mode": "text",+        "consensus_model": "claude-sonnet-5-5",+        "consensus": "agreed",+        "guards": "pin_guards 0.1: passed",+        "guard_notes": [+          "extractor flagged: Input signal 1B (input B for AND gate 1) is defined in the function table and logic diagram but is n"+        ],+        "pages_sent": 15,+        "cost_usd": 0.1778,+        "at": "2026-10-06T17:21:51"+      },+      "datasheet": {+        "url": "https://www.ti.com/lit/ds/symlink/74ac11008.pdf",+        "pages": 15,+        "sha256": "8f9e10b6605a144a",+        "source_tier": "mfr"+      },+      "cad": "KiCad official (CC-BY-SA 4.0)",+      "pins": {+        "total": 16,+        "described": 16,+        "cites_pages": true,+        "refuses_to_fabricate": true+      }+    },+    "viewers": {+      "symbol": "viewers/symbol.html",+      "footprint": "viewers/footprint.html"+    }+  },+  "visibility": "public",+  "org": "adom",+  "author": {+    "name": "Ray",+    "email": "[email protected]"+  }+}\ No newline at end of file