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74AC11008PWR
Public Made by Adomby adom
Texas Instruments Logic Gates, TSSOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdown74AC11008PWR
Texas Instruments · Logic Gates · TSSOP-16
74AC11008PWR from Texas Instruments, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1A | input | Gate 1 input A; Y = A·B, with VIH min 2.1 V at VCC = 3 V and 3.15 V at 4.5 V. |
| 2 | 1Y | output | Gate 1 output; rated for IOH of -24 mA and IOL of 24 mA at VCC = 4.5 V. |
| 3 | 2Y | output | Gate 2 output; rated for IOH of -24 mA and IOL of 24 mA at VCC = 4.5 V. |
| 4 | GND | power_in | Ground (center-pin GND configuration, tied with pin 5 to minimize switching noise). |
| 5 | GND | power_in | Ground (center-pin GND configuration, tied with pin 4 to minimize switching noise). |
| 6 | 3Y | output | Gate 3 output; rated for IOH of -24 mA and IOL of 24 mA at VCC = 4.5 V. |
| 7 | 4Y | output | Gate 4 output; rated for IOH of -24 mA and IOL of 24 mA at VCC = 4.5 V. |
| 8 | 4B | input | Gate 4 input B; Y = A·B, with VIL max 1.35 V at VCC = 4.5 V. |
| 9 | 4A | input | Gate 4 input A; Y = A·B, with input voltage range 0 V to VCC. |
| 10 | 3B | input | Gate 3 input B; Y = A·B, with input voltage range 0 V to VCC. |
| 11 | 3A | input | Gate 3 input A; Y = A·B, with input voltage range 0 V to VCC. |
| 12 | VCC | power_in | Supply voltage (center-pin VCC, tied with pin 13); recommended 3 V to 5.5 V, absolute maximum 7 V. |
| 13 | VCC | power_in | Supply voltage (center-pin VCC, tied with pin 12); recommended 3 V to 5.5 V, absolute maximum 7 V. |
| 14 | 2B | input | Gate 2 input B; Y = A·B, with input voltage range 0 V to VCC. |
| 15 | 2A | input | Gate 2 input A; Y = A·B, with input voltage range 0 V to VCC. |
| 16 | 1B | input | Gate 1 input B; Y = A·B, with input voltage range 0 V to VCC. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | TSSOP-16 |
| Category | Logic |
| Pins | 16 |
CAD (KiCad official)
- Symbol:
74AC11008PWR - Footprint:
Package_SO:TSSOP-16_4.4x5mm_P0.65mm - 3D model: TSSOP-16 (KiCad packages3D, STEP)
- 3D model files:
74ac11008pwr-etched.step/74ac11008pwr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);74ac11008pwr.step/74ac11008pwr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (15 pp, sha256
8f9e10b6605a144a, retrieved 2026-10-06, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-4-5-20251001(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).