component
74ABT125PW
Public Made by Adomby adom
Nexperia Buffers, Drivers, Receivers, Transceivers, TSSOP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
| Name | Last updated |
|---|---|
| docs | 5d ago |
| viewers | 5d ago |
| 74abt125pw-etched.glb | 5d ago |
| 74abt125pw-etched.step | 5d ago |
| 74abt125pw-hero.glb | 5d ago |
| 74abt125pw-hero.overlay.json | 5d ago |
| 74abt125pw.glb | 5d ago |
| 74abt125pw.kicad_mod | 5d ago |
| 74abt125pw.kicad_sym | 5d ago |
| 74abt125pw.lbr | 5d ago |
| 74abt125pw.step | 5d ago |
| package.json | 5d ago |
| page.json | 5d ago |
| README.md | 5d ago |
74ABT125PW
Nexperia · Buffers, Drivers, Receivers, Transceivers · TSSOP-14
74ABT125PW from Nexperia, in a TSSOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1OE | input | Output enable input (active LOW); a HIGH on 1OE forces output 1Y into the high-impedance OFF-state. |
| 2 | 1A | input | Data input for buffer 1; inputs are disabled during 3-state mode. |
| 3 | 1Y | output | Data output of buffer 1; output capability is HIGH -32 mA and LOW +64 mA. |
| 4 | 2OE | input | Output enable input (active LOW); a HIGH on 2OE forces output 2Y into the high-impedance OFF-state. |
| 5 | 2A | input | Data input for buffer 2; inputs are disabled during 3-state mode. |
| 6 | 2Y | output | Data output of buffer 2; output capability is HIGH -32 mA and LOW +64 mA. |
| 7 | GND | power_in | Ground (0 V) reference for all voltages on the device. |
| 8 | 3Y | output | Data output of buffer 3; output capability is HIGH -32 mA and LOW +64 mA. |
| 9 | 3A | input | Data input for buffer 3; inputs are disabled during 3-state mode. |
| 10 | 3OE | input | Output enable input (active LOW); a HIGH on 3OE forces output 3Y into the high-impedance OFF-state. |
| 11 | 4Y | output | Data output of buffer 4; output capability is HIGH -32 mA and LOW +64 mA. |
| 12 | 4A | input | Data input for buffer 4; inputs are disabled during 3-state mode. |
| 13 | 4OE | input | Output enable input (active LOW); a HIGH on 4OE forces output 4Y into the high-impedance OFF-state. |
| 14 | VCC | power_in | Supply voltage; recommended operating range is 4.5 V to 5.5 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Nexperia |
| Package | TSSOP-14 |
| Category | Logic |
| Pins | 14 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| supply voltage | VCC | -0.5 | 7 | V | 4 | ||
| input voltage | VI | -1.2 | 7 | V | 4 | ||
| output voltage | VO | -0.5 | 5.5 | V | output in OFF-state or HIGH-state | 4 | |
| input clamping current | IIK | -18 | mA | VI < 0 V | 4 | ||
| output clamping current | IOK | -50 | mA | VO < 0 V | 4 | ||
| output current | IO | 128 | mA | output in LOW-state | 4 | ||
| junction temperature | Tj | 150 | °C | 4 | |||
| storage temperature | Tstg | -65 | 150 | °C | 4 | ||
| total power dissipation | Ptot | 500 | mW | Tamb = -40 °C to +85 °C | 4 | ||
| supply voltage | VCC | 4.5 | 5.5 | V | 4 | ||
| input voltage | VI | 0 | V | 4 | |||
| HIGH-level input voltage | VIH | 2 | V | 4 | |||
| LOW-level input voltage | VIL | 0.8 | V | 4 | |||
| HIGH-level output current | IOH | -32 | mA | 4 | |||
| LOW-level output current | IOL | 64 | mA | 4 | |||
| input transition rise and fall rate | Δt/ΔV | 10 | ns/V | 4 | |||
| ambient temperature | Tamb | -40 | 85 | °C | in free air | 4 | |
| input clamping voltage | VIK | -0.9 | -1.2 | V | VCC = 4.5 V; IIK = -18 mA | 5 | |
| HIGH-level output voltage | VOH | 2.5 | 2.9 | V | VCC = 4.5 V; IOH = -3 mA | 5 | |
| HIGH-level output voltage | VOH | 3 | 3.4 | V | VCC = 5.0 V; IOH = -3 mA | 5 | |
| HIGH-level output voltage | VOH | 2 | 2.4 | V | VCC = 4.5 V; IOH = -32 mA | 5 | |
| LOW-level output voltage | VOL | 0.35 | 0.55 | V | VCC = 4.5 V; IOL = 64 mA; VI = VIL or VIH | 5 | |
| input leakage current | II | -1 | 0.01 | 1 | μA | VCC = 5.5 V; VI = GND or 5.5 V | 5 |
| power-off leakage current | IOFF | -100 | 5 | 100 | μA | VCC = 0.0 V; VI or VO ≤ 4.5 V | 5 |
| power-up/power-down output current | IO(pu/pd) | -50 | 5 | 50 | μA | VCC = 2.1 V; VO = 0.5 V; VI = GND or VCC; OE = don't care | 5 |
| OFF-state output current | IOZ | 1 | 50 | μA | VCC = 5.5 V; VI = VIL or VIH; VO = 2.7 V | 5 | |
| OFF-state output current | IOZ | -1 | -50 | μA | VCC = 5.5 V; VI = VIL or VIH; VO = 0.5 V | 5 | |
| output high leakage current | ICEX | 5 | 50 | μA | HIGH-state; VO = 5.5 V; VCC = 5.5 V; VI = GND or VCC | 5 | |
| output current | IO | -50 | -100 | -180 | mA | VCC = 5.5 V; VO = 2.5 V | 5 |
| supply current, outputs HIGH-state | ICC | 65 | 250 | μA | VCC = 5.5 V; VI = GND or VCC; outputs HIGH-state | 5 | |
| supply current, outputs LOW-state | ICC | 12 | 30 | mA | VCC = 5.5 V; VI = GND or VCC; outputs LOW-state | 5 | |
| supply current, outputs disabled | ICC | 65 | 250 | μA | VCC = 5.5 V; VI = GND or VCC; outputs disabled | 5 | |
| supply current per control pin, outputs enabled | ICC | 0.5 | 1.5 | mA | per control pin; VCC = 5.5 V; one control input at 3.4 V, other inputs at VCC or GND; outputs enabled | 5 | |
| supply current per control pin, outputs disabled | ICC | 50 | 250 | mA | per control pin; VCC = 5.5 V; one control input at 3.4 V, other inputs at VCC or GND; outputs disabled | 5 | |
| additional supply current | ΔICC | 0.5 | 1.5 | mA | one enable input at 3.4 V and other inputs at VCC or GND; outputs disabled | 5 | |
| LOW to HIGH propagation delay | tPLH | 1 | 2.8 | 4.6 | ns | nA to nY, see Fig. 4 | 6 |
| HIGH to LOW propagation delay | tPHL | 1 | 3.1 | 4.9 | ns | nA to nY; see Fig. 4 | 6 |
| OFF-state to HIGH propagation delay | tPZH | 1 | 3.2 | 5.9 | ns | nOE to nY; see Fig. 5 | 6 |
| OFF-state to LOW propagation delay | tPZL | 1 | 4.2 | 6.8 | ns | nOE to nY; see Fig. 5 | 6 |
| HIGH to OFF-state propagation delay | tPHZ | 1 | 4.1 | 6.2 | ns | nOE to nY; see Fig. 5 | 6 |
| LOW to OFF-state propagation delay | tPLZ | 1.5 | 2.8 | 5.5 | ns | nOE to nY; see Fig. 5 | 6 |
| input capacitance | CI | 4 | pF | VI = 0 V or VCC | 5 | ||
| output capacitance | CO | 7 | pF | outputs disabled; VO = 0 V or VCC | 5 |
CAD (KiCad official)
- Symbol:
74ABT125PW - Footprint:
Package_SO:TSSOP-14_4.4x5mm_P0.65mm - 3D model: TSSOP-14 (KiCad packages3D, STEP)
- 3D model files:
74abt125pw-etched.step/74abt125pw-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);74abt125pw.step/74abt125pw.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Nexperia datasheet (13 pp, sha256
5bdf89c407c23ab1, retrieved 2026-10-17, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).