component
74ABT08D
Public Made by Adomby adom
Nexperia Logic Gates, SO-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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74ABT08D
Nexperia · Logic Gates · SO-14
74ABT08D from Nexperia, in a SO-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1A | input | Data input 1A of gate 1; recommended input range is 0 V to VCC, with HIGH level at least 2.0 V and LOW level at most 0.8 V. |
| 2 | 1B | input | Data input 1B of gate 1; recommended input range is 0 V to VCC, with HIGH level at least 2.0 V and LOW level at most 0.8 V. |
| 3 | 1Y | output | Data output 1Y of gate 1; recommended operating IOH is -15 mA maximum (HIGH) and IOL is 20 mA maximum (LOW). |
| 4 | 2A | input | Data input 2A of gate 2; recommended input range is 0 V to VCC, with HIGH level at least 2.0 V and LOW level at most 0.8 V. |
| 5 | 2B | input | Data input 2B of gate 2; recommended input range is 0 V to VCC, with HIGH level at least 2.0 V and LOW level at most 0.8 V. |
| 6 | 2Y | output | Data output 2Y of gate 2; recommended operating IOH is -15 mA maximum (HIGH) and IOL is 20 mA maximum (LOW). |
| 7 | GND | power_in | Ground (0 V); all voltages in the datasheet are referenced to GND. |
| 8 | 3Y | output | Data output 3Y of gate 3; recommended operating IOH is -15 mA maximum (HIGH) and IOL is 20 mA maximum (LOW). |
| 9 | 3A | input | Data input 3A of gate 3; recommended input range is 0 V to VCC, with HIGH level at least 2.0 V and LOW level at most 0.8 V. |
| 10 | 3B | input | Data input 3B of gate 3; recommended input range is 0 V to VCC, with HIGH level at least 2.0 V and LOW level at most 0.8 V. |
| 11 | 4Y | output | Data output 4Y of gate 4; recommended operating IOH is -15 mA maximum (HIGH) and IOL is 20 mA maximum (LOW). |
| 12 | 4A | input | Data input 4A of gate 4; recommended input range is 0 V to VCC, with HIGH level at least 2.0 V and LOW level at most 0.8 V. |
| 13 | 4B | input | Data input 4B of gate 4; recommended input range is 0 V to VCC, with HIGH level at least 2.0 V and LOW level at most 0.8 V. |
| 14 | VCC | power_in | Supply voltage; recommended range is 4.5 V to 5.5 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Nexperia |
| Package | SO-14 |
| Category | Logic |
| Pins | 14 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| supply voltage | VCC | -0.5 | 7 | V | 3 | ||
| input voltage | VI | -1.2 | 7 | V | 3 | ||
| output voltage | VO | -0.5 | 5.5 | V | output HIGH or LOW | 3 | |
| input clamping current | IIK | -18 | mA | VI < 0 V | 3 | ||
| output clamping current | IOK | -50 | mA | VO < 0 V | 3 | ||
| output current | IO | 40 | mA | output in LOW-state | 3 | ||
| junction temperature | Tj | 150 | °C | 3 | |||
| storage temperature | Tstg | -65 | 150 | °C | 3 | ||
| supply voltage | VCC | 4.5 | 5.5 | V | 3 | ||
| input voltage | VI | 0 | V | 3 | |||
| HIGH-level input voltage | VIH | 2 | V | 3 | |||
| LOW-level input voltage | VIL | 0.8 | V | 3 | |||
| HIGH-level output current | IOH | -15 | mA | 3 | |||
| LOW-level output current | IOL | 20 | mA | 3 | |||
| input transition rise and fall rate | Δt/ΔV | 0 | 5 | ns/V | 3 | ||
| ambient temperature | Tamb | -40 | 85 | °C | in free air | 3 | |
| input clamping voltage | VIK | -1.2 | -0.9 | V | 25 °C; VCC = 4.5 V; IIK = -18 mA | 4 | |
| input clamping voltage | VIK | -1.2 | V | -40 °C to +85 °C; VCC = 4.5 V; IIK = -18 mA | 4 | ||
| HIGH-level output voltage | VOH | 2.5 | 2.9 | V | 25 °C; VCC = 4.5 V; IOH = -15 mA; VI = VIL or VIH | 4 | |
| HIGH-level output voltage | VOH | 2.5 | V | -40 °C to +85 °C; VCC = 4.5 V; IOH = -15 mA; VI = VIL or VIH | 4 | ||
| LOW-level output voltage | VOL | 0.35 | 0.5 | V | 25 °C; VCC = 4.5 V; IOL = 20 mA; VI = VIL or VIH | 4 | |
| LOW-level output voltage | VOL | 0.5 | V | -40 °C to +85 °C; VCC = 4.5 V; IOL = 20 mA; VI = VIL or VIH | 4 | ||
| input leakage current | II | -1 | 0.01 | 1 | μA | 25 °C; VCC = 5.5 V; VI = GND or 5.5 V | 4 |
| input leakage current | II | -1 | 1 | μA | -40 °C to +85 °C; VCC = 5.5 V; VI = GND or 5.5 V | 4 | |
| power-off leakage current | IOFF | -100 | 5 | 100 | μA | 25 °C; VCC = 0 V; VI or VO ≤ 4.5 V | 4 |
| power-off leakage current | IOFF | -100 | 100 | μA | -40 °C to +85 °C; VCC = 0 V; VI or VO ≤ 4.5 V | 4 | |
| output high leakage current | ICEX | 5 | 50 | μA | 25 °C; HIGH-state; VO = 5.5 V; VCC = 5.5 V; VI = GND or VCC | 4 | |
| output high leakage current | ICEX | 50 | μA | -40 °C to +85 °C; HIGH-state; VO = 5.5 V; VCC = 5.5 V; VI = GND or VCC | 4 | ||
| output current | IO | -50 | -75 | -180 | mA | 25 °C; VCC = 5.5 V; VO = 2.5 V [1] | 4 |
| output current | IO | -50 | -180 | mA | -40 °C to +85 °C; VCC = 5.5 V; VO = 2.5 V [1] | 4 | |
| supply current | ICC | 2 | 50 | μA | 25 °C; VCC = 5.5 V; VI = GND or VCC | 4 | |
| supply current | ICC | 50 | μA | -40 °C to +85 °C; VCC = 5.5 V; VI = GND or VCC | 4 | ||
| additional supply current | ΔICC | 0.25 | 500 | μA | 25 °C; per input pin; VCC = 5.5 V; one input at 3.4 V; other inputs at VCC or GND [2] | 4 | |
| additional supply current | ΔICC | 500 | μA | -40 °C to +85 °C; per input pin; VCC = 5.5 V; one input at 3.4 V; other inputs at VCC or GND [2] | 4 | ||
| LOW to HIGH propagation delay | tPLH | 1 | 2.4 | 3.4 | ns | 25 °C; VCC = 5.0 V; nA, nB to nY; see Fig. 4 | 4 |
| LOW to HIGH propagation delay | tPLH | 1 | 4 | ns | -40 °C to +85 °C; VCC = 5.0 V ± 0.5 V; nA, nB to nY; see Fig. 4 | 4 | |
| HIGH to LOW propagation delay | tPHL | 1 | 1.9 | 2.8 | ns | 25 °C; VCC = 5.0 V; nA, nB to nY; see Fig. 4 | 4 |
| HIGH to LOW propagation delay | tPHL | 1 | 3 | ns | -40 °C to +85 °C; VCC = 5.0 V ± 0.5 V; nA, nB to nY; see Fig. 4 | 4 | |
| output skew time | tsk(o) | 0.4 | 0.5 | ns | 25 °C; VCC = 5.0 V | 4 | |
| output skew time | tsk(o) | 0.5 | ns | -40 °C to +85 °C; VCC = 5.0 V ± 0.5 V | 4 |
CAD (KiCad official)
- Symbol:
74ABT08D - Footprint:
Adom_Gen:Nexperia_74 - 3D model: SO-14 (KiCad packages3D, STEP)
- 3D model files:
74abt08d-etched.step/74abt08d-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);74abt08d.step/74abt08d.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Nexperia datasheet (10 pp, sha256
e2d2da5070beb9b6, retrieved 2026-10-17, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# 74ABT08D
**Nexperia** · Logic Gates · SO-14
74ABT08D from Nexperia, in a SO-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1A | input | Data input 1A of gate 1; recommended input range is 0 V to VCC, with HIGH level at least 2.0 V and LOW level at most 0.8 V. |
| 2 | 1B | input | Data input 1B of gate 1; recommended input range is 0 V to VCC, with HIGH level at least 2.0 V and LOW level at most 0.8 V. |
| 3 | 1Y | output | Data output 1Y of gate 1; recommended operating IOH is -15 mA maximum (HIGH) and IOL is 20 mA maximum (LOW). |
| 4 | 2A | input | Data input 2A of gate 2; recommended input range is 0 V to VCC, with HIGH level at least 2.0 V and LOW level at most 0.8 V. |
| 5 | 2B | input | Data input 2B of gate 2; recommended input range is 0 V to VCC, with HIGH level at least 2.0 V and LOW level at most 0.8 V. |
| 6 | 2Y | output | Data output 2Y of gate 2; recommended operating IOH is -15 mA maximum (HIGH) and IOL is 20 mA maximum (LOW). |
| 7 | GND | power_in | Ground (0 V); all voltages in the datasheet are referenced to GND. |
| 8 | 3Y | output | Data output 3Y of gate 3; recommended operating IOH is -15 mA maximum (HIGH) and IOL is 20 mA maximum (LOW). |
| 9 | 3A | input | Data input 3A of gate 3; recommended input range is 0 V to VCC, with HIGH level at least 2.0 V and LOW level at most 0.8 V. |
| 10 | 3B | input | Data input 3B of gate 3; recommended input range is 0 V to VCC, with HIGH level at least 2.0 V and LOW level at most 0.8 V. |
| 11 | 4Y | output | Data output 4Y of gate 4; recommended operating IOH is -15 mA maximum (HIGH) and IOL is 20 mA maximum (LOW). |
| 12 | 4A | input | Data input 4A of gate 4; recommended input range is 0 V to VCC, with HIGH level at least 2.0 V and LOW level at most 0.8 V. |
| 13 | 4B | input | Data input 4B of gate 4; recommended input range is 0 V to VCC, with HIGH level at least 2.0 V and LOW level at most 0.8 V. |
| 14 | VCC | power_in | Supply voltage; recommended range is 4.5 V to 5.5 V. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Nexperia |
| Package | SO-14 |
| Category | Logic |
| Pins | 14 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| supply voltage | VCC | -0.5 | | 7 | V | | 3 |
| input voltage | VI | -1.2 | | 7 | V | | 3 |
| output voltage | VO | -0.5 | | 5.5 | V | output HIGH or LOW | 3 |
| input clamping current | IIK | -18 | | | mA | VI < 0 V | 3 |
| output clamping current | IOK | -50 | | | mA | VO < 0 V | 3 |
| output current | IO | | | 40 | mA | output in LOW-state | 3 |
| junction temperature | Tj | | | 150 | °C | | 3 |
| storage temperature | Tstg | -65 | | 150 | °C | | 3 |
| supply voltage | VCC | 4.5 | | 5.5 | V | | 3 |
| input voltage | VI | 0 | | | V | | 3 |
| HIGH-level input voltage | VIH | 2 | | | V | | 3 |
| LOW-level input voltage | VIL | | | 0.8 | V | | 3 |
| HIGH-level output current | IOH | -15 | | | mA | | 3 |
| LOW-level output current | IOL | | | 20 | mA | | 3 |
| input transition rise and fall rate | Δt/ΔV | 0 | | 5 | ns/V | | 3 |
| ambient temperature | Tamb | -40 | | 85 | °C | in free air | 3 |
| input clamping voltage | VIK | -1.2 | -0.9 | | V | 25 °C; VCC = 4.5 V; IIK = -18 mA | 4 |
| input clamping voltage | VIK | -1.2 | | | V | -40 °C to +85 °C; VCC = 4.5 V; IIK = -18 mA | 4 |
| HIGH-level output voltage | VOH | 2.5 | 2.9 | | V | 25 °C; VCC = 4.5 V; IOH = -15 mA; VI = VIL or VIH | 4 |
| HIGH-level output voltage | VOH | 2.5 | | | V | -40 °C to +85 °C; VCC = 4.5 V; IOH = -15 mA; VI = VIL or VIH | 4 |
| LOW-level output voltage | VOL | | 0.35 | 0.5 | V | 25 °C; VCC = 4.5 V; IOL = 20 mA; VI = VIL or VIH | 4 |
| LOW-level output voltage | VOL | | | 0.5 | V | -40 °C to +85 °C; VCC = 4.5 V; IOL = 20 mA; VI = VIL or VIH | 4 |
| input leakage current | II | -1 | 0.01 | 1 | μA | 25 °C; VCC = 5.5 V; VI = GND or 5.5 V | 4 |
| input leakage current | II | -1 | | 1 | μA | -40 °C to +85 °C; VCC = 5.5 V; VI = GND or 5.5 V | 4 |
| power-off leakage current | IOFF | -100 | 5 | 100 | μA | 25 °C; VCC = 0 V; VI or VO ≤ 4.5 V | 4 |
| power-off leakage current | IOFF | -100 | | 100 | μA | -40 °C to +85 °C; VCC = 0 V; VI or VO ≤ 4.5 V | 4 |
| output high leakage current | ICEX | | 5 | 50 | μA | 25 °C; HIGH-state; VO = 5.5 V; VCC = 5.5 V; VI = GND or VCC | 4 |
| output high leakage current | ICEX | | | 50 | μA | -40 °C to +85 °C; HIGH-state; VO = 5.5 V; VCC = 5.5 V; VI = GND or VCC | 4 |
| output current | IO | -50 | -75 | -180 | mA | 25 °C; VCC = 5.5 V; VO = 2.5 V [1] | 4 |
| output current | IO | -50 | | -180 | mA | -40 °C to +85 °C; VCC = 5.5 V; VO = 2.5 V [1] | 4 |
| supply current | ICC | | 2 | 50 | μA | 25 °C; VCC = 5.5 V; VI = GND or VCC | 4 |
| supply current | ICC | | | 50 | μA | -40 °C to +85 °C; VCC = 5.5 V; VI = GND or VCC | 4 |
| additional supply current | ΔICC | | 0.25 | 500 | μA | 25 °C; per input pin; VCC = 5.5 V; one input at 3.4 V; other inputs at VCC or GND [2] | 4 |
| additional supply current | ΔICC | | | 500 | μA | -40 °C to +85 °C; per input pin; VCC = 5.5 V; one input at 3.4 V; other inputs at VCC or GND [2] | 4 |
| LOW to HIGH propagation delay | tPLH | 1 | 2.4 | 3.4 | ns | 25 °C; VCC = 5.0 V; nA, nB to nY; see Fig. 4 | 4 |
| LOW to HIGH propagation delay | tPLH | 1 | | 4 | ns | -40 °C to +85 °C; VCC = 5.0 V ± 0.5 V; nA, nB to nY; see Fig. 4 | 4 |
| HIGH to LOW propagation delay | tPHL | 1 | 1.9 | 2.8 | ns | 25 °C; VCC = 5.0 V; nA, nB to nY; see Fig. 4 | 4 |
| HIGH to LOW propagation delay | tPHL | 1 | | 3 | ns | -40 °C to +85 °C; VCC = 5.0 V ± 0.5 V; nA, nB to nY; see Fig. 4 | 4 |
| output skew time | tsk(o) | | 0.4 | 0.5 | ns | 25 °C; VCC = 5.0 V | 4 |
| output skew time | tsk(o) | | | 0.5 | ns | -40 °C to +85 °C; VCC = 5.0 V ± 0.5 V | 4 |
## CAD (KiCad official)
- Symbol: `74ABT08D`
- Footprint: `Adom_Gen:Nexperia_74`
- 3D model: SO-14 (KiCad packages3D, STEP)
- 3D model files: `74abt08d-etched.step` / `74abt08d-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `74abt08d.step` / `74abt08d.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Nexperia datasheet](https://assets.nexperia.com/documents/data-sheet/74ABT08D.pdf) (10 pp, sha256 `e2d2da5070beb9b6`, retrieved 2026-10-17, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/74abt08d-datasheet.pdf)