component

621SDCGI

Public Made by Adom

by adom

RENESAS Clock Buffers, Drivers, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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621SDCGI

RENESAS · Clock Buffers, Drivers · SOIC-8

621SDCGI from RENESAS, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 ICLK input Clock input with internal pull-up resistor; VIH min 0.7xVDD and VIL max 0.3xVDD (switching threshold VDD/2).
2 Q1 output Clock output 1, non-inverting, tri-stated when OE is low.
3 Q2 output Clock output 2, non-inverting, tri-stated when OE is low.
4 Q3 output Clock output 3, non-inverting, tri-stated when OE is low.
5 Q4 output Clock output 4, non-inverting, tri-stated when OE is low.
6 GND power_in Connect to ground; decoupling capacitor of 0.01uF goes between VDD (pin 7) and this pin.
7 VDD power_in Connect +1.8V, +2.5V or +3.3V (1.71V to 3.465V operating range) with a 0.01uF decoupling capacitor to GND.
8 OE input Output Enable with internal pull-up resistor; tri-states outputs when low.

Key specifications

Parameter Value
Manufacturer RENESAS
Package SOIC-8
Category RTC/Clock Chip
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply Voltage VDD 3.465 V 3
All Inputs and Outputs -0.5 3.465 V 3
Ambient Operating Temperature, Extended -40 105 C 3
Storage Temperature -65 150 C 3
Junction Temperature 125 C 3
Soldering Temperature 260 C 3
Ambient Operating Temperature, Extended -40 105 C 3
Power Supply Voltage VDD 1.71 3.465 V measured in respect to GND 3
Operating Voltage (1.8V) VDD 1.71 1.89 V VDD=1.8 V ±5% 4
Input High Voltage, ICLK (1.8V) VIH 1.89 V Note 1 4
Output High Voltage (1.8V) VOH 1.3 V IOH = -10 mA 4
Output Low Voltage (1.8V) VOL 0.35 V IOL = 10 mA 4
Operating Supply Current (1.8V) IDD 13 mA No load, 135 MHz 4
Nominal Output Impedance (1.8V) ZO 17 Ω 4
Input Capacitance (1.8V) CIN 5 pF OE pin 4
Operating Voltage (2.5V) VDD 2.375 2.625 V VDD=2.5 V ±5% 4
Input High Voltage, ICLK (2.5V) VIH 2.625 V Note 1 4
Output High Voltage (2.5V) VOH 1.8 V IOH = -16 mA 4
Output Low Voltage (2.5V) VOL 0.5 V IOL = 16 mA 4
Operating Supply Current (2.5V) IDD 18 mA No load, 135 MHz 4
Nominal Output Impedance (2.5V) ZO 17 Ω 4
Input Capacitance (2.5V) CIN 5 pF OE pin 4
Operating Voltage (3.3V) VDD 3.135 3.465 V VDD=3.3 V ±5% 4
Input High Voltage, ICLK (3.3V) VIH 3.465 V Note 1 4
Output High Voltage (3.3V) VOH 2.2 V IOH = -25 mA 4
Output Low Voltage (3.3V) VOL 0.7 V IOL = 25 mA 4
Operating Supply Current (3.3V) IDD 22 mA No load, 135 MHz 4
Nominal Output Impedance (3.3V) ZO 17 Ω 4
Input Capacitance (3.3V) CIN 5 pF OE pin 4
Output Frequency (1.8V) 200 MHz 5pF load, Note 4 5
Output Clock Rise Time (1.8V) tOR 0.6 1 ns 0.36 to 1.44 V 5
Output Clock Fall Time (1.8V) tOF 0.6 1 ns 1.44 to 0.36V 5
Start-up Time (1.8V) tSTART-UP 2 ms Part start-up time for valid outputs after VDD ramp-up 5
Propagation Delay (1.8V) 1.5 2 4 ns 135 MHz, Note 1 5
Buffer Additive Phase Jitter, RMS (1.8V) 0.05 ps 125MHz, Integration range: 12kHz-20MHz 5
Output to Output Skew (1.8V) 50 65 ps Rising edges at VDD/2, Note 2 5
Output Enable Time (1.8V) tEN 3 cycles CL < 5pF 5
Output Disable Time (1.8V) tDIS 3 cycles CL < 5pF 5
Output Frequency (2.5V) 200 MHz 5pF load, Note 4 5
Output Clock Rise Time (2.5V) tOR 0.6 1 ns 0.5 to 2.0V 5
Output Clock Fall Time (2.5V) tOF 0.6 1 ns 2.0 to 0.5V 5
Start-up Time (2.5V) tSTART-UP 2 ms Part start-up time for valid outputs after VDD ramp-up 5
Propagation Delay (2.5V) 1.8 2.5 4.5 ns 135 MHz, Note 1 5
Buffer Additive Phase Jitter, RMS (2.5V) 0.05 ps 125MHz, Integration range: 12kHz-20MHz 5
Output to Output Skew (2.5V) 50 65 ps Rising edges at VDD/2, Note 2 5
Output Enable Time (2.5V) tEN 3 cycles CL < 5pF 5
Output Disable Time (2.5V) tDIS 3 cycles CL < 5pF 5
Output Frequency (3.3V) 200 MHz 5pF load, Note 4 5
Output Clock Rise Time (3.3V) tOR 0.6 1 ns 0.66 to 2.64V 5
Output Clock Fall Time (3.3V) tOF 0.6 1 ns 2.64 to 0.66V 5
Start-up Time (3.3V) tSTART-UP 2 ms Part start-up time for valid outputs after VDD ramp-up 5
Propagation Delay (3.3V) 1.5 2 4 ns 135 MHz, Note 1 5
Buffer Additive Phase Jitter, RMS (3.3V) 0.05 ps 125MHz, Integration range: 12kHz-20MHz 5
Output to Output Skew (3.3V) 50 65 ps Rising edges at VDD/2, Note 2 5
Output Enable Time (3.3V) tEN 3 cycles CL < 5pF 5
Output Disable Time (3.3V) tDIS 3 cycles CL < 5pF 5
Thermal Resistance Junction to Ambient θJA 150 C/W Still air 7
Thermal Resistance Junction to Ambient θJA 140 C/W 1 m/s air flow 7
Thermal Resistance Junction to Ambient θJA 120 C/W 3 m/s air flow 7
Thermal Resistance Junction to Case θJC 40 C/W 7

CAD (KiCad official)

  • Symbol: 621SDCGI
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOIC-8 (KiCad packages3D, STEP)
  • 3D model files: 621sdcgi-etched.step / 621sdcgi-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); 621sdcgi.step / 621sdcgi.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: RENESAS datasheet (13 pp, sha256 1bcc0eb6007be34b, retrieved 2026-10-23, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF