component
5V9885TPFGI8
Public Made by Adomby adom
RENESAS Clock Generators / Frequency Synthesizers / PLL, TQFP-32(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
main
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{
"schema_version": 1,
"type": "component",
"slug": "5v9885tpfgi8",
"title": "5V9885TPFGI8",
"brief": "RENESAS Clock Generators / Frequency Synthesizers / PLL, TQFP-32(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
"version": "0.1.0",
"license": "CC-BY-SA-4.0",
"tags": [
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"clock and timing",
"5v9885tpfgi8",
"factory-2.0.0",
"extractor-text"
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"component": {
"mpn": "5V9885TPFGI8",
"manufacturer": "RENESAS",
"package": "TQFP-32(7x7)",
"pin_count": 32,
"category": "Clock and Timing",
"subcategory": "Clock Generators / Frequency Synthesizers / PLL",
"datasheet": "https://datasheet.lcsc.com/datasheet/pdf/4eff62c9d652766d49049e3d339f9cac.pdf",
"parts": {
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"model_3d_step": "5v9885tpfgi8-etched.step",
"model_3d_step_plain": "5v9885tpfgi8.step",
"lbr": "5v9885tpfgi8.lbr"
},
"distributor_links": {
"lcsc": "C2664386",
"digikey": "5V9885TPFGI8-ND",
"mouser": "972-5V9885TPFGI8"
},
"distributor_check": {
"checked_at": "2026-10-31T00:04:10Z",
"source": "Component Ocean /api/assign-pns",
"digikey": {
"pn": "5V9885TPFGI8-ND",
"status": "found",
"lifecycle": "Obsolete"
},
"mouser": {
"pn": "972-5V9885TPFGI8",
"status": "found",
"lifecycle": "Obsolete"
}
},
"pins": [
{
"number": "1",
"name": "CLKIN",
"type": "input",
"description": "LVTTL input clock; the reference clock can come from one of the two redundant clock inputs."
},
{
"number": "2",
"name": "GND",
"type": "power_in",
"description": "Ground."
},
{
"number": "3",
"name": "GOUT1/LOSS_CLKIN",
"type": "output",
"description": "Multi-purpose LVTTL output that can be programmed as the LOSS_CLKIN signal."
},
{
"number": "4",
"name": "XTALIN/REFIN",
"type": "input",
"description": "LVTTL reference crystal input or external reference clock input; crystal frequency range is 8MHz to 50MHz."
},
{
"number": "5",
"name": "XTALOUT",
"type": "output",
"description": "LVTTL crystal output for reference crystal feedback."
},
{
"number": "6",
"name": "OUT1",
"type": "output",
"description": "LVTTL configurable clock output 1, which can also be used to buffer the reference clock."
},
{
"number": "7",
"name": "VDD",
"type": "power_in",
"description": "3.3V power supply."
},
{
"number": "8",
"name": "OUT3",
"type": "output",
"description": "LVTTL configurable clock output 3."
},
{
"number": "9",
"name": "GND",
"type": "power_in",
"description": "Ground."
},
{
"number": "10",
"name": "OUT4",
"type": "output",
"description": "Configurable clock output 4; single-ended LVTTL, or differential LVDS/LVPECL when combined with the complementary OUT4 pin."
},
{
"number": "11",
"name": "OUT4",
"type": "output",
"description": "Configurable complementary clock output 4; single-ended, or differential LVDS/LVPECL when combined with the OUT4 pin."
},
{
"number": "12",
"name": "VDD",
"type": "power_in",
"description": "3.3V power supply."
},
{
"number": "13",
"name": "OUT6",
"type": "output",
"description": "LVTTL configurable clock output 6."
},
{
"number": "14",
"name": "GND",
"type": "power_in",
"description": "Ground."
},
{
"number": "15",
"name": "OUT5",
"type": "output",
"description": "Configurable clock output 5; single-ended LVTTL, or differential LVDS/LVPECL when combined with the complementary OUT5 pin."
},
{
"number": "16",
"name": "OUT5",
"type": "output",
"description": "Configurable complementary clock output 5; single-ended, or differential LVDS/LVPECL when combined with the OUT5 pin."
},
{
"number": "17",
"name": "VDD",
"type": "power_in",
"description": "3.3V power supply."
},
{
"number": "18",
"name": "GND",
"type": "power_in",
"description": "Ground."
},
{
"number": "19",
"name": "GIN0/SDAT/TDI",
"type": "input",
"description": "Multi-purpose LVTTL input for frequency control, I2C SDAT, or JTAG TDI; has a weak internal 100KΩ pull-down."
},
{
"number": "20",
"name": "GIN1/SCLK/TCK",
"type": "input",
"description": "Multi-purpose LVTTL input for frequency control, I2C SCLK, or JTAG TCK; has a weak internal 100KΩ pull-down."
},
{
"number": "21",
"name": "GIN5/CLK_SEL",
"type": "input",
"description": "Multi-purpose LVTTL input for frequency control or input clock selector; has a weak internal 100KΩ pull-down."
},
{
"number": "22",
"name": "I2C/JTAG",
"type": "input",
"description": "3-level static input selecting I2C (HIGH), MFC mode (MID) or JTAG programming (LOW); must be tied to VDD or GND or left floating and is not hot-insertable or overvoltage tolerant."
},
{
"number": "23",
"name": "VDD",
"type": "power_in",
"description": "3.3V power supply."
},
{
"number": "24",
"name": "GIN2/TMS",
"type": "input",
"description": "Multi-purpose LVTTL input for frequency control or JTAG TMS; has a weak internal 100KΩ pull-down."
},
{
"number": "25",
"name": "GIN4/TRST",
"type": "input",
"description": "Multi-purpose LVTTL input for frequency control or JTAG TRST; has a weak internal 100KΩ pull-down."
},
{
"number": "26",
"name": "VDD",
"type": "power_in",
"description": "3.3V power supply."
},
{
"number": "27",
"name": "GIN3/SUSPEND",
"type": "input",
"description": "Multi-purpose LVTTL input for frequency control or suspend mode control input (active HIGH); has a weak internal 100KΩ pull-down."
},
{
"number": "28",
"name": "SHUTDOWN/OE",
"type": "input",
"description": "LVTTL input that enables/disables the outputs or powers down the chip; polarity set by the SP bit (0x1C), default active HIGH."
},
{
"number": "29",
"name": "OUT2",
"type": "output",
"description": "LVTTL configurable clock output 2."
},
{
"number": "30",
"name": "GND",
"type": "power_in",
"description": "Ground."
},
{
"number": "31",
"name": "GOUT0/TDO/LOSS_LOCK",
"type": "output",
"description": "Multi-purpose LVTTL output that can be programmed as the PLL LOCK signal, LOSS_LOCK, or JTAG TDO."
},
{
"number": "32",
"name": "VDD",
"type": "power_in",
"description": "3.3V power supply."
}
],
"provenance": {
"extractor": "extract_pins 0.3",
"factory_chain": {
"factory": "2.0.0",
"extractor": "extract_pins 0.3",
"primary_model": "claude-haiku-5-5",
"primary_mode": "text",
"consensus_model": "claude-sonnet-5-5",
"consensus": "agreed",
"guards": "pin_guards 0.1: passed",
"guard_notes": [
"extractor flagged: The text extraction does not preserve the complementary overbar on the OUT4 and OUT5 pin names, so b; The TQFP pin configuration drawing is garbled in the text; the pinout was taken from the PF32 column; Pin 22 name is garbled in the text as 'I C/JTAG'; it was read as I2C/JTAG from the pin description t"
],
"pages_sent": 8,
"cost_usd": 0.0584,
"at": "2026-10-31T00:03:59"
},
"datasheet": {
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"pages": 40,
"sha256": "7a2f92f1db89a39b",
"source_tier": "lcsc"
},
"cad": "KiCad official (CC-BY-SA 4.0)",
"pins": {
"total": 32,
"described": 32,
"cites_pages": true,
"refuses_to_fabricate": true
}
},
"viewers": {
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},
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},
"metadata": {
"specs": {
"Manufacturer": "RENESAS",
"Package": "TQFP-32(7x7)",
"Category": "Clock and Timing",
"Pins": "32"
},
"characteristics": {
"version": 1,
"source": "datasheet",
"datasheet_sha256": "7a2f92f1db89a39b26434740810101a6e7fbff528b2c81b4996e15925b5e6128",
"rows": [
{
"name": "Internal Power Supply Voltage",
"symbol": "VDD",
"kind": "absolute_maximum",
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"min": -0.5,
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{
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"max": null,
"conditions": "Not to exceed 4.6V; printed as VDD + 0.5",
"source_page": 27,
"source": "datasheet"
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{
"name": "Junction Temperature",
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{
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"min": 3,
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{
"name": "Power Supply Voltage for LVDS/LVPECL",
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{
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"min": -40,
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{
"name": "Maximum Load Capacitance (LVTTL only)",
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"kind": "recommended_operating",
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"min": null,
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"max": 15,
"conditions": "LVTTL only",
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{
"name": "External Reference Crystal",
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"min": 8,
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"source_page": 27,
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{
"name": "External Reference Clock, Industrial",
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"unit": "MHz",
"min": 1,
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"max": 400,
"conditions": "",
"source_page": 27,
"source": "datasheet"
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{
"name": "Power-up time for all VDDs to reach minimum specified voltage",
"symbol": "tPU",
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"min": 0.05,
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"conditions": "Power ramps must be monotonic",
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{
"name": "Quiescent VDD Power Supply Current",
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"kind": "electrical",
"unit": "mA",
"min": null,
"typ": 6,
"max": 12,
"conditions": "REF = LOW; Outputs enabled, All outputs unloaded",
"source_page": 28,
"source": "datasheet"
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{
"name": "Dynamic VDD Power Supply Current per Output",
"symbol": "IDDD",
"kind": "electrical",
"unit": "µA/MHz",
"min": null,
"typ": 40,
"max": 60,
"conditions": "VDD = Max., CL = 0pF",
"source_page": 28,
"source": "datasheet"
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{
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"unit": "mA",
"min": null,
"typ": 26,
"max": 40,
"conditions": "REFERENCE CLOCK = 33MHz, CL = 15pf",
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"typ": 80,
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"conditions": "REFERENCE CLOCK = 133MHz, CL = 15pf",
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"conditions": "REFERENCE CLOCK = 200MHz, CL = 15pf",
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{
"name": "Quiescent VDD Power Supply Current (LVDS outputs)",
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"conditions": "REF = LOW; Outputs enabled, All outputs unloaded",
"source_page": 29,
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{
"name": "Quiescent VDD Power Supply Current (LVPECL outputs)",
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"typ": 86,
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"conditions": "REF = LOW; Outputs enabled, All outputs unloaded",
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"source": "datasheet"
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{
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"conditions": "REFERENCE CLOCK = 400MHz, CL = 5pf",
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{
"name": "Total Power VDD Supply Current (LVPECL outputs)",
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"max": 210,
"conditions": "REFERENCE CLOCK = 400MHz, CL = 5pf",
"source_page": 29,
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{
"name": "Input LOW Voltage Level (I2C/JTAG 3-Level Input)",
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"kind": "electrical",
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{
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"conditions": "VIN = VDD/2, MID Level",
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{
"name": "3-Level Input DC Current (LOW level)",
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{
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"kind": "electrical",
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"max": null,
"conditions": "VOH = VDD - 0.5, VDD = 3.3V ± 0.3V",
"source_page": 28,
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{
"name": "Output LOW Current",
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"kind": "electrical",
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"conditions": "VOL = 0.5V, VDD = 3.3V ± 0.3V",
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{
"name": "Input Voltage HIGH",
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"kind": "electrical",
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"min": 2,
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"conditions": "",
"source_page": 28,
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{
"name": "Input Voltage LOW",
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"typ": null,
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{
"name": "Input HIGH Current",
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"conditions": "VIN = VDD",
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{
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"min": null,
"typ": null,
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"conditions": "VIN = 0V",
"source_page": 28,
"source": "datasheet"
},
{
"name": "Output Leakage Current",
"symbol": "IOZD",
"kind": "electrical",
"unit": "µA",
"min": null,
"typ": null,
"max": 10,
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