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5V9885TPFGI8

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RENESAS Clock Generators / Frequency Synthesizers / PLL, TQFP-32(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentclock and timing5v9885tpfgi8factory-2.0.0extractor-text

Verified 5V9885TPFGI8

by Ray · last 31 Oct 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

31 Oct 2026RayPublished by the parts factory: tier lcsc, 32 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: 5V9885TPFGI8 · TQFP-32(7x7) · 32 pins
  • ✓copper: 32 copper pads, none touching another net
  • ✓datasheet: all 32 pin names found in the 40-page datasheet
  • ✓distributor: lcsc C2664386, digikey 5V9885TPFGI8-ND, mouser 972-5V9885TPFGI8
  • ✓family: TQFP-32_7x7mm_P0.8mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-z6jnlfy6/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 32 pins = 32 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 32 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ 5v9885tpfgi8.kicad_sym✓ 5v9885tpfgi8.kicad_mod✓ 5v9885tpfgi8.step
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Ray Publish 0.1.0 ed3a643 11h ago

5V9885TPFGI8

RENESAS · Clock Generators / Frequency Synthesizers / PLL · TQFP-32(7x7)

5V9885TPFGI8 from RENESAS, in a TQFP-32(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 CLKIN input LVTTL input clock; the reference clock can come from one of the two redundant clock inputs.
2 GND power_in Ground.
3 GOUT1/LOSS_CLKIN output Multi-purpose LVTTL output that can be programmed as the LOSS_CLKIN signal.
4 XTALIN/REFIN input LVTTL reference crystal input or external reference clock input; crystal frequency range is 8MHz to 50MHz.
5 XTALOUT output LVTTL crystal output for reference crystal feedback.
6 OUT1 output LVTTL configurable clock output 1, which can also be used to buffer the reference clock.
7 VDD power_in 3.3V power supply.
8 OUT3 output LVTTL configurable clock output 3.
9 GND power_in Ground.
10 OUT4 output Configurable clock output 4; single-ended LVTTL, or differential LVDS/LVPECL when combined with the complementary OUT4 pin.
11 OUT4 output Configurable complementary clock output 4; single-ended, or differential LVDS/LVPECL when combined with the OUT4 pin.
12 VDD power_in 3.3V power supply.
13 OUT6 output LVTTL configurable clock output 6.
14 GND power_in Ground.
15 OUT5 output Configurable clock output 5; single-ended LVTTL, or differential LVDS/LVPECL when combined with the complementary OUT5 pin.
16 OUT5 output Configurable complementary clock output 5; single-ended, or differential LVDS/LVPECL when combined with the OUT5 pin.
17 VDD power_in 3.3V power supply.
18 GND power_in Ground.
19 GIN0/SDAT/TDI input Multi-purpose LVTTL input for frequency control, I2C SDAT, or JTAG TDI; has a weak internal 100KΩ pull-down.
20 GIN1/SCLK/TCK input Multi-purpose LVTTL input for frequency control, I2C SCLK, or JTAG TCK; has a weak internal 100KΩ pull-down.
21 GIN5/CLK_SEL input Multi-purpose LVTTL input for frequency control or input clock selector; has a weak internal 100KΩ pull-down.
22 I2C/JTAG input 3-level static input selecting I2C (HIGH), MFC mode (MID) or JTAG programming (LOW); must be tied to VDD or GND or left floating and is not hot-insertable or overvoltage tolerant.
23 VDD power_in 3.3V power supply.
24 GIN2/TMS input Multi-purpose LVTTL input for frequency control or JTAG TMS; has a weak internal 100KΩ pull-down.
25 GIN4/TRST input Multi-purpose LVTTL input for frequency control or JTAG TRST; has a weak internal 100KΩ pull-down.
26 VDD power_in 3.3V power supply.
27 GIN3/SUSPEND input Multi-purpose LVTTL input for frequency control or suspend mode control input (active HIGH); has a weak internal 100KΩ pull-down.
28 SHUTDOWN/OE input LVTTL input that enables/disables the outputs or powers down the chip; polarity set by the SP bit (0x1C), default active HIGH.
29 OUT2 output LVTTL configurable clock output 2.
30 GND power_in Ground.
31 GOUT0/TDO/LOSS_LOCK output Multi-purpose LVTTL output that can be programmed as the PLL LOCK signal, LOSS_LOCK, or JTAG TDO.
32 VDD power_in 3.3V power supply.

Key specifications

Parameter Value
Manufacturer RENESAS
Package TQFP-32(7x7)
Category Clock and Timing
Pins 32

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Internal Power Supply Voltage VDD -0.5 4.6 V 27
Input Voltage VI -0.5 4.6 V 27
Output Voltage VO -0.5 V Not to exceed 4.6V; printed as VDD + 0.5 27
Junction Temperature TJ 150 °C 27
Storage Temperature TSTG -65 150 °C 27
Power Supply Voltage for LVTTL VDD 3 3.3 3.6 V 27
Power Supply Voltage for LVDS/LVPECL VDD 3.135 3.3 3.465 V 27
Operating Temperature, Ambient TA -40 85 °C 27
Maximum Load Capacitance (LVTTL only) CLOAD_OUT 15 pF LVTTL only 27
External Reference Crystal FIN 8 50 MHz 27
External Reference Clock, Industrial FIN 1 400 MHz 27
Power-up time for all VDDs to reach minimum specified voltage tPU 0.05 5 ms Power ramps must be monotonic 27
Quiescent VDD Power Supply Current IDDQ 6 12 mA REF = LOW; Outputs enabled, All outputs unloaded 28
Dynamic VDD Power Supply Current per Output IDDD 40 60 µA/MHz VDD = Max., CL = 0pF 28
Total Power VDD Supply Current ITOT 26 40 mA REFERENCE CLOCK = 33MHz, CL = 15pf 28
Total Power VDD Supply Current ITOT 80 120 mA REFERENCE CLOCK = 133MHz, CL = 15pf 28
Total Power VDD Supply Current ITOT 112 170 mA REFERENCE CLOCK = 200MHz, CL = 15pf 28
Quiescent VDD Power Supply Current (LVDS outputs) IDDQ 68 90 mA REF = LOW; Outputs enabled, All outputs unloaded 29
Quiescent VDD Power Supply Current (LVPECL outputs) IDDQ 86 110 mA REF = LOW; Outputs enabled, All outputs unloaded 29
Total Power VDD Supply Current (LVDS outputs) ITOT 122 190 mA REFERENCE CLOCK = 400MHz, CL = 5pf 29
Total Power VDD Supply Current (LVPECL outputs) ITOT 140 210 mA REFERENCE CLOCK = 400MHz, CL = 5pf 29
Input LOW Voltage Level (I2C/JTAG 3-Level Input) VILL 0.4 V I2C/JTAG 3-Level Input 28
3-Level Input DC Current (HIGH level) I3 200 µA VIN = VDD, HIGH Level 28
3-Level Input DC Current (MID level) I3 -50 50 µA VIN = VDD/2, MID Level 28
3-Level Input DC Current (LOW level) I3 -200 µA VIN = GND, LOW Level 28
Output HIGH Current IOH 12 24 mA VOH = VDD - 0.5, VDD = 3.3V ± 0.3V 28
Output LOW Current IOL 12 24 mA VOL = 0.5V, VDD = 3.3V ± 0.3V 28
Input Voltage HIGH VIH 2 V 28
Input Voltage LOW VIL 0.8 V 28
Input HIGH Current IIH 10 µA VIN = VDD 28
Input LOW Current IIL 10 µA VIN = 0V 28
Output Leakage Current IOZD 10 µA 3-state outputs 28
Differential Output Voltage for the TRUE binary state VOT (+) 247 454 mV 29
Differential Output Voltage for the FALSE binary state VOT (-) -247 -454 mV 29
Change in VOT between Complimentary Output States ΔVOT 50 mV 29
Output Common Mode Voltage (Offset Voltage) VOS 1.125 1.2 1.375 V 29
Change in VOS between Complimentary Output States ΔVOS 50 mV 29
Outputs Short Circuit Current IOS 9 24 mA VOUT+ or VOUT- = 0V or VDD 29
Differential Outputs Short Circuit Current IOSD 6 12 mA VOUT+ = VOUT- 29
Peak to Peak Output Voltage Swing (LVPECL) VSWING 0.55 0.93 V 29
Input Leakage Current (I2C) IIN -1 1 µA 26
Output LOW Voltage (I2C) VOL 0.4 V IOL = 3 mA 26
Input Frequency Limit fIN 400 MHz Spread spectrum generation = OFF 30
Output Frequency, Single Ended Clock output limit (LVTTL) 1/t1 0.0049 200 MHz Spread spectrum generation = OFF 30
Output Frequency, Differential Clock output limit (LVPECL/LVDS) 1/t1 0.0049 500 MHz Spread spectrum generation = OFF 30
VCO Frequency fVCO 10 1200 MHz VCO operating Frequency Range 30
PFD Frequency fPFD 0.4 400 MHz PFD operating Frequency Range 30
Loop Bandwidth fBW 0.03 40 MHz Based on loop filter resistor and capacitor values 30
Input Duty Cycle t2 40 60 % Duty Cycle for Input 30
Output Duty Cycle t3 45 55 % Measured at VDD/2, FOUT ≤200MHz 30
Output Duty Cycle t3 40 60 % Measured at VDD/2, FOUT > 200MHz 30
Output three-state timing after SHUTDOWN/OE switches t6 150 ns Time for output to enter or leave three-state mode; printed max is 150 + 1/FOUTX 30
Clock Jitter, peak-to-peak period t7 150 ps fPFD > 20MHz; CLK outputs measured at VDD/2; guaranteed by design, not production tested 30
Output Skew t8 150 ps Skew between output to output on the same bank (bank 4 and bank 5 only) 30
Lock Time from Power-up t9 10 20 ms PLL Lock Time from Power-up 30
Lock time from shutdown mode t10 20 100 µs PLL Lock time from shutdown mode 30
Amount of Spread Value (Programmable) - Center Spread fSPREAD -2 2 % Center spread 30

CAD (KiCad official)

  • Symbol: 5V9885TPFGI8
  • Footprint: Package_QFP:TQFP-32_7x7mm_P0.8mm
  • 3D model: TQFP-32(7x7) (KiCad packages3D, STEP)
  • 3D model files: 5v9885tpfgi8-etched.step / 5v9885tpfgi8-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); 5v9885tpfgi8.step / 5v9885tpfgi8.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: RENESAS datasheet (40 pp, sha256 7a2f92f1db89a39b, retrieved 2026-10-31, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF