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5V41066PGGI8

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RENESAS Clock Generators / Frequency Synthesizers / PLL, TSSOP-20. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentclock and timing5v41066pggi8factory-2.0.0extractor-text

Verified 5V41066PGGI8

by Ray · last 31 Oct 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

31 Oct 2026RayPublished by the parts factory: tier lcsc, 20 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: 5V41066PGGI8 · TSSOP-20 · 20 pins
  • ✓copper: 20 copper pads, none touching another net
  • ✓datasheet: all 20 pin names found in the 15-page datasheet
  • ✓distributor: lcsc C2667838, digikey 6690-5V41066PGGI8TR-ND, mouser 972-5V41066PGGI8
  • ✓family: TSSOP-20_4.4x6.5mm_P0.65mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-7_qobl00/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • ✓package_fit: height and body within the datasheet's package drawing (datasheet p.12)
  • ✓pads: 20 pins = 20 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 20 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ 5v41066pggi8.kicad_sym✓ 5v41066pggi8.kicad_mod✓ 5v41066pggi8.step
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Ray Publish 0.1.0 4f8457b 11h ago

5V41066PGGI8

RENESAS · Clock Generators / Frequency Synthesizers / PLL · TSSOP-20

5V41066PGGI8 from RENESAS, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VDDXD power_in Connect to the +3.3 V digital supply, which is specified at 3.135 V to 3.465 V.
2 S0 input Spread spectrum select pin #0, which sets spread % and output frequency per the selection table; has an internal pull-up resistor.
3 S1 input Spread spectrum select pin #1, which sets spread % and output frequency per the selection table; has an internal pull-up resistor.
4 S2 input Spread spectrum select pin #2, which sets spread % and output frequency per the selection table; has an internal pull-up resistor.
5 X1 input Connect to a fundamental mode crystal or clock input; crystal load capacitors from X1 to ground are used to tune initial accuracy.
6 X2 output Connect to a fundamental mode crystal or leave open.
7 PD input Powers down all PLLs and tri-states the outputs when low; has an internal pull-up resistor.
8 OE input Enables the outputs when High and tri-states the outputs when Low; has an internal pull-up resistor.
9 GND power_in Connect to digital ground.
10 IREF output Precision resistor (Rr = 475 Ω, 1%, for a 50 Ω board impedance) attached to this pin sets the internal current reference, giving IREF of 2.32 mA.
11 CLKD output Selectable 100/200 MHz spread spectrum differential complement output clock D.
12 CLKD output Selectable 100/200 MHz spread spectrum differential true output clock D.
13 CLKC output Selectable 100/200 MHz spread spectrum differential complement output clock C.
14 CLKC output Selectable 100/200 MHz spread spectrum differential true output clock C.
15 VDDODA power_in Connect to the +3.3 V analog supply, which is specified at 3.135 V to 3.465 V.
16 GND power_in Connect to analog ground.
17 CLKB output Selectable 100/200 MHz spread spectrum differential complement output clock B.
18 CLKB output Selectable 100/200 MHz spread spectrum differential true output clock B.
19 CLKA output Selectable 100/200 MHz spread spectrum differential complement output clock A.
20 CLKA output Selectable 100/200 MHz spread spectrum differential true output clock A.

Key specifications

Parameter Value
Manufacturer RENESAS
Package TSSOP-20
Category Clock and Timing
Pins 20

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply Voltage V 3.135 3.3 3.465 V 9
Input High Voltage VIH 2.2 V 9
Input Low Voltage VIL 0.8 V 9
Input Leakage Current IIL -5 5 μA 0 < Vin < VDD 9
Operating Supply Current IDD 115 125 mA @100 MHz; RS=33Ω, RP=50Ω, CL=2 pF 9
Operating Supply Current, OE low IDDOE 42 48 mA OE =Low 9
Power-down Supply Current IDDPD 350 500 μA No load, PD =Low 9
Output Frequency 25 200 MHz HCSL termination 10
Output Frequency 25 100 MHz LVDS termination 10
Crossing Point Voltage, Absolute 250 550 mV Absolute 10
Cycle-to-Cycle Jitter 100 ps 1
Output to Output Skew 50 ps 1
Duty Cycle 45 55 % 10
Modulation Frequency 30 32.9 33 kHz Spread spectrum 10
Rise Time tOR 175 700 ps From 0.175 V to 0.525 V 10
Fall Time tOF 175 700 ps From 0.525 V to 0.175 V 10
Output Enable Time 50 100 ns All outputs 10
Output Disable Time 50 100 ns All outputs 10
Spread Spectrum Transition Time tSPREAD 7 30 ms Stabilization time after spread spectrum changes 10
Jitter, Phase PLL (PCIe Gen1) tjphasePLL 30 86 ps (p-p) PCIe Gen1 10
Jitter, Phase LO (PCIe Gen2) tjphaseLO 0.76 3 ps (RMS) PCIe Gen2, 10 kHz < f < 1.5 MHz 10
Jitter, Phase HIGH (PCIe Gen2) tjphaseHIGH 2 3.1 ps (RMS) PCIe Gen2, 1.5 MHz < f < Nyquist (50 MHz) 10
Supply Voltage, VDD, VDDA VDD, VDDA 5.5 V 9
All Inputs and Outputs -0.5 V 9
Ambient Operating Temperature (industrial) -40 85 °C 9
Storage Temperature -65 150 °C 9
Junction Temperature 125 °C 9
Soldering Temperature 260 °C 9
ESD Protection (Input) 2000 V HBM 9
Thermal Resistance, Junction to Ambient θJA 93 °C/W Still air 11
Thermal Resistance, Junction to Ambient θJA 78 °C/W 1 m/s air flow 11
Thermal Resistance, Junction to Ambient θJA 65 °C/W 3 m/s air flow 11
Thermal Resistance, Junction to Case θJC 20 °C/W 11

CAD (KiCad official)

  • Symbol: 5V41066PGGI8
  • Footprint: Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm
  • 3D model: TSSOP-20 (KiCad packages3D, STEP)
  • 3D model files: 5v41066pggi8-etched.step / 5v41066pggi8-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); 5v41066pggi8.step / 5v41066pggi8.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: RENESAS datasheet (15 pp, sha256 f66a4a80cbf05513, retrieved 2026-10-31, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF