component
5PB1216NDGK8
Public Made by Adomby adom
RENESAS Clock Buffers, Drivers, QFN-20-EP(3x3). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdown5PB1216NDGK8
RENESAS · Clock Buffers, Drivers · QFN-20-EP(3x3)
5PB1216NDGK8 from RENESAS, in a QFN-20-EP(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | OE2 | input | Active-high output enable for CLKOUT2 with an internal 120kΩ pull-down. |
| 2 | OE3 | input | Active-high output enable for CLKOUT3 with an internal 120kΩ pull-down. |
| 3 | VDD | power_in | Supply pin; connect 2.5V or 3.3V for the 5PB1216, with a 0.01µF bypass capacitor on each VDD pin. |
| 4 | GND | power_in | Power supply ground; use a separate ground via for each GND pin. |
| 5 | OE6 | input | Active-high output enable for CLKOUT6 with an internal 120kΩ pull-down. |
| 6 | OE4 | input | Active-high output enable for CLKOUT4 with an internal 120kΩ pull-down. |
| 7 | OE5 | input | Active-high output enable for CLKOUT5 with an internal 120kΩ pull-down. |
| 8 | OE_OSC | output | Crystal oscillator enable pin that is low if all OE pins are low and otherwise high, enabling the reference oscillator, per the Enable Function Truth Table. |
| 9 | VDD | power_in | Supply pin; connect 2.5V or 3.3V for the 5PB1216, with a 0.01µF bypass capacitor on each VDD pin. |
| 10 | CLKOUT6 | output | Clock output 6 at the same frequency as CLKIN. |
| 11 | CLKOUT5 | output | Clock output 5 at the same frequency as CLKIN. |
| 12 | GND | power_in | Power supply ground; use a separate ground via for each GND pin. |
| 13 | CLKOUT4 | output | Clock output 4 at the same frequency as CLKIN. |
| 14 | CLKOUT3 | output | Clock output 3 at the same frequency as CLKIN. |
| 15 | VDD | power_in | Supply pin; connect 2.5V or 3.3V for the 5PB1216, with a 0.01µF bypass capacitor on each VDD pin. |
| 16 | CLKOUT2 | output | Clock output 2 at the same frequency as CLKIN. |
| 17 | CLKOUT1 | output | Clock output 1 at the same frequency as CLKIN. |
| 18 | GND | power_in | Power supply ground; use a separate ground via for each GND pin. |
| 19 | OE1 | input | Active-high output enable for CLKOUT1 with an internal 120kΩ pull-down. |
| 20 | CLKIN | input | Reference input pin; connect to an LVCMOS input or a TCXO. |
| 21 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | RENESAS |
| Package | QFN-20-EP(3x3) |
| Category | Clock and Timing |
| Pins | 21 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Operating Voltage (2.5V) | VDD | 2.375 | 2.625 | V | VDD = 2.5V ±5% | 4 | |
| Operating Voltage (3.3V) | VDD | 3.135 | 3.465 | V | VDD = 3.3V ±5% | 5 | |
| Operating Supply Current, outputs enabled (2.5V) | IDD | 12.58 | 16.3 | mA | CLKIN = 26MHz, all outputs enabled, VDD = 2.5V | 4 | |
| Operating Supply Current, outputs disabled (2.5V) | IDD | 0.01 | 0.04 | mA | CLKIN = Low or High, all outputs disabled, VDD = 2.5V | 4 | |
| Operating Supply Current, outputs enabled (3.3V) | IDD | 16.87 | 21.72 | mA | CLKIN = 26MHz, all outputs enabled, VDD = 3.3V | 5 | |
| Operating Supply Current, outputs disabled (3.3V) | IDD | 0.22 | 0.7 | mA | CLKIN = Low or High, all outputs disabled, VDD = 3.3V | 5 | |
| Input Capacitance | CIN | 5 | pF | ICLK, OE pin | 5 | ||
| Nominal Output Impedance | ZO | 17 | Ω | 5 | |||
| Input Frequency (2.5V) | 0 | 200 | MHz | VDD = 2.5V | 6 | ||
| Output Rise Time (2.5V) | tOR | 0.6 | 1 | ns | 0.5 to 2.0V, CL = 5pF | 6 | |
| Output Fall Time (2.5V) | tOF | 0.6 | 1 | ns | 2.0 to 0.5V, CL = 5pF | 6 | |
| Propagation Delay (2.5V) | 1.7 | 2.2 | 2.7 | ns | With rail to rail input clock | 6 | |
| Buffer Additive Phase Jitter, RMS (2.5V, TCXO) | 280 | fs | 26MHz TCXO clipped sine wave input, 12kHz to 20MHz | 6 | |||
| Buffer Additive Phase Jitter, RMS (2.5V, LVCMOS) | 30 | fs | 125MHz LVCMOS input, 12kHz to 20MHz | 6 | |||
| Output to Output Skew (2.5V) | tSKEWO−O | 20 | 50 | ps | Rising edges at VDD/2 | 6 | |
| Device to Device Skew (2.5V) | tSKEWD-D | 200 | ps | Rising edges at VDD/2 | 6 | ||
| Output Enable/Disable Time (2.5V) | tEN/tDIS | 3 | cycles | CL < 5pF | 6 | ||
| Start-up Time (2.5V) | tSTART-UP | 2 | ms | Part start-up time for valid outputs after VDD ramp-up | 6 | ||
| Clipped Sine Wave Input Voltage Swing (2.5V) | VINpp | 0.8 | V | VDD = 2.5V, AC coupling and bias circuit | 6 | ||
| Input Frequency (3.3V) | 0 | 200 | MHz | VDD = 3.3V | 7 | ||
| Output Rise Time (3.3V) | tOR | 0.6 | 1 | ns | 0.66 to 2.64V, CL = 5pF | 7 | |
| Output Fall Time (3.3V) | tOF | 0.6 | 1 | ns | 2.64 to 0.66V, CL = 5pF | 7 | |
| Propagation Delay (3.3V) | 1.4 | 1.9 | 2.4 | ns | With rail to rail input clock | 7 | |
| Buffer Additive Phase Jitter, RMS (3.3V, TCXO) | 377 | fs | 26MHz TCXO clipped sine wave input, 12kHz to 20MHz | 7 | |||
| Buffer Additive Phase Jitter, RMS (3.3V, LVCMOS) | 18 | fs | 125MHz LVCMOS input, 12kHz to 20MHz | 7 | |||
| Output to Output Skew (3.3V) | tSKEWO−O | 20 | 50 | ps | Rising edges at VDD/2 | 7 | |
| Device to Device Skew (3.3V) | tSKEWD-D | 200 | ps | Rising edges at VDD/2 | 7 | ||
| Output Enable/Disable Time (3.3V) | tEN/tDIS | 3 | cycles | CL < 5pF | 7 | ||
| Start-up Time (3.3V) | tSTART-UP | 2 | ms | Part start-up time for valid outputs after VDD ramp-up | 7 | ||
| Clipped Sine Wave Input Voltage Swing (3.3V) | VINpp | 0.5 | V | VDD = 3.3V, AC coupling and bias circuit | 7 | ||
| Supply Voltage | VDD | 3.8 | V | 3 | |||
| Output Enable and All Inputs/Outputs | -0.5 | V | -0.5 V to VDD + 0.5 V | 3 | |||
| Ambient Operating Temperature | -40 | 105 | °C | extended | 3 | ||
| Storage Temperature | -65 | 150 | °C | 3 | |||
| Junction Temperature | 125 | °C | 3 | ||||
| Soldering Temperature | 260 | °C | 3 |
CAD (KiCad official)
- Symbol:
5PB1216NDGK8 - Footprint:
Package_DFN_QFN:UQFN-20-1EP_3x3mm_P0.4mm_EP1.85x1.85mm - 3D model: QFN-20-EP(3x3) (KiCad packages3D, STEP)
- 3D model files:
5pb1216ndgk8-etched.step/5pb1216ndgk8-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);5pb1216ndgk8.step/5pb1216ndgk8.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: RENESAS datasheet (16 pp, sha256
0b03cd5320c59ca9, retrieved 2026-10-22, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).