component

5PB1108PGGK8

Public Made by Adom

by adom

RENESAS Clock Buffers, Drivers, TSSOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentclock and timing5pb1108pggk8factory-2.0.0extractor-text

Verified 5PB1108PGGK8

by Ray · last 30 Oct 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

30 Oct 2026RayPublished by the parts factory: tier mfr, 16 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: 5PB1108PGGK8 · TSSOP-16 · 16 pins
  • ✓copper: 16 copper pads, none touching another net
  • ✓datasheet: all 16 pin names found in the 41-page datasheet
  • ✓distributor: lcsc C1511198, digikey 6690-5PB1108PGGK8TR-ND, mouser 972-5PB1108PGGK8
  • ✓family: TSSOP-16_4.4x5mm_P0.65mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-r2hfbztp/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): the datasheet dimensions give no height or body size to compare (datasheet p.29)
  • ✓pads: 16 pins = 16 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 16 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ 5pb1108pggk8.kicad_sym✓ 5pb1108pggk8.kicad_mod✓ 5pb1108pggk8.step
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Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 18h ago
viewers 5pb1108pggk8: viewers · Ray 18h ago
5pb1108pggk8-etched.glb Publish 0.1.0 · Ray 18h ago
5pb1108pggk8-etched.step 5pb1108pggk8: factory component page (tier=mfr) · Ray 18h ago
5pb1108pggk8-hero.glb 5pb1108pggk8: hero GLB from the etched model (keeps the MPN mark) · Ray 18h ago
5pb1108pggk8-hero.overlay.json Publish 0.1.0 · Ray 18h ago
5pb1108pggk8.glb Publish 0.1.0 · Ray 18h ago
5pb1108pggk8.kicad_mod Publish 0.1.0 · Ray 18h ago
5pb1108pggk8.kicad_sym Publish 0.1.0 · Ray 18h ago
5pb1108pggk8.lbr Publish 0.1.0 · Ray 18h ago
5pb1108pggk8.step Publish 0.1.0 · Ray 18h ago
package.json Publish 0.1.0 · Ray 18h ago
page.json Set visibility: public · Ray 18h ago
README.md Publish 0.1.0 · Ray 18h ago
verification.json Verified: Published by the parts factory: tier mfr, 16 pins · Ray 18h ago

5PB1108PGGK8

RENESAS · Clock Buffers, Drivers · TSSOP-16

5PB1108PGGK8 from RENESAS, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 CLKIN input LVCMOS clock input that is 3.3 V tolerant, with VIH of 0.7 x VDD minimum and VIL of 0.3 x VDD maximum, and an absolute input voltage range of -0.4 V to 3.465 V.
2 1G input Output enable: when 1G is low all Yn outputs are held low, and when high the outputs follow CLKIN; VIH is 2.0 V minimum and VIL is 0.8 V maximum at a 3.3 V supply.
3 Y0 output LVCMOS clock output with a nominal output impedance of 50 Ω, rated VOH of 2.4 V minimum at -12 mA and VOL of 0.7 V maximum at 12 mA at a 3.3 V supply.
4 GND power_in Ground reference for the device.
5 VDD power_in Supply pin; the power supply voltage measured with respect to GND must be between 1.71 V and 3.465 V.
6 Y4 output LVCMOS clock output with a nominal output impedance of 50 Ω, rated VOH of 2.4 V minimum at -12 mA and VOL of 0.7 V maximum at 12 mA at a 3.3 V supply.
7 GND power_in Ground reference for the device.
8 Y6 output LVCMOS clock output with a nominal output impedance of 50 Ω, rated VOH of 2.4 V minimum at -12 mA and VOL of 0.7 V maximum at 12 mA at a 3.3 V supply.
9 Y7 output LVCMOS clock output with a nominal output impedance of 50 Ω, rated VOH of 2.4 V minimum at -12 mA and VOL of 0.7 V maximum at 12 mA at a 3.3 V supply.
10 VDD power_in Supply pin; the power supply voltage measured with respect to GND must be between 1.71 V and 3.465 V.
11 Y5 output LVCMOS clock output with a nominal output impedance of 50 Ω, rated VOH of 2.4 V minimum at -12 mA and VOL of 0.7 V maximum at 12 mA at a 3.3 V supply.
12 GND power_in Ground reference for the device.
13 Y2 output LVCMOS clock output with a nominal output impedance of 50 Ω, rated VOH of 2.4 V minimum at -12 mA and VOL of 0.7 V maximum at 12 mA at a 3.3 V supply.
14 VDD power_in Supply pin; the power supply voltage measured with respect to GND must be between 1.71 V and 3.465 V.
15 Y3 output LVCMOS clock output with a nominal output impedance of 50 Ω, rated VOH of 2.4 V minimum at -12 mA and VOL of 0.7 V maximum at 12 mA at a 3.3 V supply.
16 Y1 output LVCMOS clock output with a nominal output impedance of 50 Ω, rated VOH of 2.4 V minimum at -12 mA and VOL of 0.7 V maximum at 12 mA at a 3.3 V supply.

Key specifications

Parameter Value
Manufacturer RENESAS
Package TSSOP-16
Category Clock and Timing
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Input Voltage, CLKIN -0.4 3.465 V 5
Supply Voltage VDD 3.8 V 5
Output Enable and All Outputs voltage -0.4 V 5
Ambient Operating Temperature (Extended and Automotive Grade 2) -40 105 C 5
Storage Temperature -65 150 C 5
Junction Temperature 125 C 5
Soldering Temperature 260 C 5
Ambient Operating Temperature (Extended and Automotive Grade 2) -40 105 C 5
Power Supply Voltage (measured in respect to GND) 1.71 3.465 V 5
Operating Voltage (VDD=1.8V ±5%) VDD 1.71 1.8 1.89 V 7
Operating Voltage (VDD=2.5V ±5%) VDD 2.375 2.5 2.625 V 9
Operating Voltage (VDD=3.3V ±5%) VDD 3.135 3.3 3.465 V 11
Input High Voltage, 1G (VDD=1.8V) VIH 1.6 V 7
Input Low Voltage, 1G (VDD=1.8V) VIL 0.6 V 7
Output High Voltage (VDD=1.8V) VOH 1.4 V IOH = -5mA. 7
Output Low Voltage (VDD=1.8V) VOL 0.4 V IOL = 5mA. 7
Operating Supply Current, 5PB1108 (VDD=1.8V) IDD 20 23 mA 100MHz, no load, 25°C. 7
Input High Voltage, 1G (VDD=2.5V) VIH 1.8 V 9
Input Low Voltage, 1G (VDD=2.5V) VIL 0.7 V 9
Output High Voltage (VDD=2.5V) VOH 1.9 V IOH = -8mA. 9
Output Low Voltage (VDD=2.5V) VOL 0.5 V IOL = 8mA. 9
Operating Supply Current, 5PB1108 (VDD=2.5V) IDD 27 31 mA 100MHz, no load, 25°C. 9
Input High Voltage, 1G (VDD=3.3V) VIH 2 V 11
Input Low Voltage, 1G (VDD=3.3V) VIL 0.8 V 11
Output High Voltage (VDD=3.3V) VOH 2.4 V IOH = -12mA. 11
Output Low Voltage (VDD=3.3V) VOL 0.7 V IOL = 12mA. 11
Operating Supply Current, 5PB1108 (VDD=3.3V) IDD 35 38 mA 100MHz, no load, 25°C. 11
Input High Leakage IIH 5 µA VIN = VDD 7
Input Low Leakage IIL 5 µA VIN = 0V 7
Input Frequency 0 200 MHz 13
Output Rise Time (2pF load), VDD=1.8V tOR 0.5 0.75 ns 0.36V to 1.44V, CL = 2pF. 13
Output Fall Time (2pF load), VDD=1.8V tOF 0.5 0.75 ns 1.44V to 0.36V, CL = 2pF. 13
Output Rise Time (5pF load), VDD=1.8V tOR 0.8 1 ns 0.36V to 1.44V, CL = 5pF. 13
Output Fall Time (5pF load), VDD=1.8V tOF 0.8 1 ns 1.44V to 0.36V, CL = 5pF. 13
Propagation Delay, VDD=1.8V tPD 1.5 2.5 ns Rail-to-rail input clock. 13
Output to Output Skew, 5PB1108/10, VDD=1.8V 45 65 ps Rising edges at VDD/2; between any 2 outputs with equal loading. 13
Device to Device Skew 200 ps Rising edges at VDD/2. 13
Start-up Time 3 ms Part start-up time for valid outputs after VDD ramp-up. 13
Output Enable Time tEN 3 cycles CL < 5pF. 13
Output Disable Time tDIS 3 cycles CL < 5pF. 13
Output Rise Time (2pF load), VDD=2.5V tOR 0.4 0.7 ns 0.5V to 2.0V, CL = 2pF. 15
Output Fall Time (2pF load), VDD=2.5V tOF 0.4 0.7 ns 2.0V to 0.5V, CL = 2pF. 15
Output Rise Time (5pF load), VDD=2.5V tOR 0.75 1 ns 0.5V to 2.0V, CL = 5pF. 15
Output Fall Time (5pF load), VDD=2.5V tOF 0.75 1 ns 2.0V to 0.5V, CL = 5pF. 15
Propagation Delay, 5PB1106/08, VDD=2.5V tPD 2 3.3 ns Rail-to-rail input clock. 15
Output to Output Skew, 5PB1108/10, VDD=2.5V 45 65 ps Rising edges at VDD/2; between any 2 outputs with equal loading. 15
Output Rise Time (2pF load), VDD=3.3V tOR 0.45 0.6 ns 0.66V to 2.64V, CL = 2pF. 17
Output Fall Time (2pF load), VDD=3.3V tOF 0.45 0.6 ns 2.64V to 0.66V, CL = 2pF. 17
Output Rise Time (5pF load), VDD=3.3V tOR 0.7 1 ns 0.66V to 2.64V, CL = 5pF. 17
Output Fall Time (5pF load), VDD=3.3V tOF 0.7 1 ns 2.64V to 0.66V, CL = 5pF. 17
Propagation Delay, 5PB1106/08, VDD=3.3V tPD 1.7 2.7 ns Rail-to-rail input clock. 17
Output to Output Skew, 5PB1108/10, VDD=3.3V 45 65 ps Rising edges at VDD/2; between any 2 outputs with equal loading. 17
Output Impedance, Nominal ZO 50 Ω 7
Input Capacitance, CLKIN and 1G pins CIN 5 pF CLKIN, 1G pin. 7
Buffer Additive Phase Jitter, RMS 0.05 ps 156.25MHz, Integration Range: 12kHz-20MHz. 13
Duty Cycle tDC 50 % Duty cycle on outputs will match incoming clock duty cycle when VIH on CLKIN equals VDD. 13
Thermal Resistance, Junction-to-Ambient, 16-TSSOP (5PB1108PGG) ΘJA 80.9 °C/W still air 6
Thermal Resistance, Junction-to-Case, 16-TSSOP (5PB1108PGG) ΘJC 43.3 °C/W still air 6
Thermal Resistance, Junction-to-Board, 16-TSSOP (5PB1108PGG) ΘJB 60.1 °C/W still air 6

CAD (KiCad official)

  • Symbol: 5PB1108PGGK8
  • Footprint: Package_SO:TSSOP-16_4.4x5mm_P0.65mm
  • 3D model: TSSOP-16 (KiCad packages3D, STEP)
  • 3D model files: 5pb1108pggk8-etched.step / 5pb1108pggk8-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); 5pb1108pggk8.step / 5pb1108pggk8.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: RENESAS datasheet (41 pp, sha256 a39aca2d9b003582, retrieved 2026-10-30, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF