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5PB1102CMGI8

Public Made by Adom

by adom

RENESAS Clock Buffers, Drivers, WDFN-8(2x2). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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5PB1102CMGI8

RENESAS · Clock Buffers, Drivers · WDFN-8(2x2)

5PB1102CMGI8 from RENESAS, in a WDFN-8(2x2). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 CLKIN input LVCMOS clock input, 3.3V tolerant (absolute max -0.4V to 3.465V), with VIH of 0.7 × VDD, VIL of 0.3 × VDD and 200MHz maximum input frequency.
2 1G input LVCMOS clock output enable input; Yn outputs are low when 1G is low and follow CLKIN when 1G is high.
3 Y0 output LVCMOS clock output 0 with 50Ω nominal output impedance (integrated serial termination).
4 GND power_in Ground.
5 NC unconnected No connect.
6 VDD power_in Supply voltage of 1.8V to 3.3V (1.71V to 3.465V recommended operating range, 3.8V absolute maximum).
7 NC unconnected No connect.
8 Y1 output LVCMOS clock output 1 with 50Ω nominal output impedance (integrated serial termination).
9 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer RENESAS
Package WDFN-8(2x2)
Category Clock and Timing
Pins 9

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply Voltage VDD 3.8 V 5
Output Enable and All Outputs -0.4 V -0.4 V to VDD + 0.5 V 5
Input Voltage, CLKIN -0.4 3.465 V 5
Storage Temperature -65 150 C 5
Junction Temperature 125 C 5
Soldering Temperature 260 C 5
Ambient Operating Temperature (Industrial) -40 85 C 5
Power Supply Voltage VDD 1.71 3.465 V measured in respect to GND 5
Thermal Resistance Junction to Ambient, 8-DFN ΘJA 120.2 °C/W still air 6
Thermal Resistance Junction to Case, 8-DFN ΘJC 99.4 °C/W still air 6
Thermal Resistance Junction to Board, 8-DFN ΘJB 63.3 °C/W still air 6
Operating Voltage (1.8V) VDD 1.71 1.8 1.89 V 7
Input High Voltage, 1G (1.8V) VIH 1.6 V 1G; max printed as VDD 7
Input Low Voltage, 1G (1.8V) VIL 0.6 V 1G 7
Output High Voltage (1.8V) VOH 1.4 V IOH = -5mA 7
Output Low Voltage (1.8V) VOL 0.4 V IOL = 5mA 7
Operating Supply Current, 5PB1102 (1.8V) IDD 6 8 mA 100MHz, no load, 25°C 7
Input High Leakage IIH 5 µA VIN = VDD 7
Input Low Leakage IIL 5 µA VIN = 0V 7
Operating Voltage (2.5V) VDD 2.375 2.5 2.625 V 9
Input High Voltage, 1G (2.5V) VIH 1.8 V 1G; max printed as VDD 9
Input Low Voltage, 1G (2.5V) VIL 0.7 V 1G 9
Output High Voltage (2.5V) VOH 1.9 V IOH = -8mA 9
Output Low Voltage (2.5V) VOL 0.5 V IOL = 8mA 9
Operating Supply Current, 5PB1102 (2.5V) IDD 9 11 mA 100MHz, no load, 25°C 9
Input High Leakage (2.5V) IIH 5 µA VIN = VDD 9
Operating Voltage (3.3V) VDD 3.135 3.3 3.465 V 11
Input High Voltage, 1G (3.3V) VIH 2 V 1G; max printed as VDD 11
Input Low Voltage, 1G (3.3V) VIL 0.8 V 1G 11
Output High Voltage (3.3V) VOH 2.4 V IOH = -12mA 11
Output Low Voltage (3.3V) VOL 0.7 V IOL = 12mA 11
Operating Supply Current, 5PB1102 (3.3V) IDD 12 13 mA 100MHz, no load, 25°C 11
Input High Leakage (3.3V) IIH 5 µA VIN = VDD 11
Nominal Output Impedance ZO 50 Ω 7
Input Capacitance CIN 5 pF CLKIN, 1G pin 7
Input Frequency 0 200 MHz 13
Start-up Time tSTART-UP 3 ms Part start-up time for valid outputs after VDD ramp-up 13
Device to Device Skew 200 ps Rising edges at VDD/2 13
Output Enable Time tEN 3 cycles CL < 5pF 13
Output Rise Time, 2pF load (1.8V) tOR 0.5 0.75 ns 0.36V to 1.44V, CL = 2pF 13
Output Fall Time, 2pF load (1.8V) tOF 0.5 0.75 ns 1.44V to 0.36V, CL = 2pF 13
Output Rise Time, 5pF load (1.8V) tOR 0.8 1 ns 0.36V to 1.44V, CL = 5pF 13
Output Fall Time, 5pF load (1.8V) tOF 0.8 1 ns 1.44V to 0.36V, CL = 5pF 13
Propagation Delay (1.8V) tPD 1.5 2.5 ns With rail-to-rail input clock 13
Buffer Additive Phase Jitter, RMS (1.8V) 0.05 ps 156.25MHz, Integration Range: 12kHz-20MHz 13
Output to Output Skew, 5PB1102/04 (1.8V) 35 50 ps Rising edges at VDD/2 13
Output Rise Time, 2pF load (2.5V) tOR 0.4 0.7 ns 0.5V to 2.0V, CL = 2pF 15
Output Fall Time, 2pF load (2.5V) tOF 0.4 0.7 ns 2.0V to 0.5V, CL = 2pF 15
Output Rise Time, 5pF load (2.5V) tOR 0.75 1 ns 0.5V to 2.0V, CL = 5pF 15
Output Fall Time, 5pF load (2.5V) tOF 0.75 1 ns 2.0V to 0.5V, CL = 5pF 15
Propagation Delay, 5PB1102/04 (2.5V) tPD 1.9 2.9 ns With rail-to-rail input clock 15
Buffer Additive Phase Jitter, RMS (2.5V) 0.05 ps 156.25MHz, Integration Range: 12kHz-20MHz 15
Output to Output Skew, 5PB1102/04 (2.5V) 35 50 ps Rising edges at VDD/2 15
Output Rise Time, 2pF load (3.3V) tOR 0.45 0.6 ns 0.66V to 2.64V, CL = 2pF 17
Output Fall Time, 2pF load (3.3V) tOF 0.45 0.6 ns 2.64V to 0.66V, CL = 2pF 17
Output Rise Time, 5pF load (3.3V) tOR 0.7 1 ns 0.66V to 2.64V, CL = 5pF 17
Output Fall Time, 5pF load (3.3V) tOF 0.7 1 ns 2.64V to 0.66V, CL = 5pF 17
Propagation Delay, 5PB1102/04 (3.3V) tPD 1.7 2.4 ns With rail-to-rail input clock 17
Buffer Additive Phase Jitter, RMS (3.3V) 0.05 ps 156.25MHz, Integration Range: 12kHz-20MHz 17
Output to Output Skew, 5PB1102/04 (3.3V) 35 50 ps Rising edges at VDD/2 17

CAD (KiCad official)

  • Symbol: 5PB1102CMGI8
  • Footprint: Package_DFN_QFN:WDFN-8-1EP_2x2mm_P0.5mm_EP0.8x1.2mm
  • 3D model: WDFN-8(2x2), generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 0.75 mm nominal WSON height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
  • 3D model files: 5pb1102cmgi8-etched.step / 5pb1102cmgi8-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); 5pb1102cmgi8.step / 5pb1102cmgi8.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: RENESAS datasheet (41 pp, sha256 a39aca2d9b003582, retrieved 2026-10-23, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF