component
5P49V5923B000NLGI
Public Made by Adomby adom
RENESAS Clock Generators / Frequency Synthesizers / PLL, QFN-24(4x4). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
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PCB Footprint
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Datasheet
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README
markdown5P49V5923B000NLGI
RENESAS · Clock Generators / Frequency Synthesizers / PLL · QFN-24(4x4)
5P49V5923B000NLGI from RENESAS, in a QFN-24(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | CLKIN | input | Differential clock input with a weak 100 kohm internal pull-down. |
| 2 | CLKINB | input | Complementary differential clock input with a weak 100 kohm internal pull-down. |
| 3 | XOUT | output | Crystal oscillator interface output, used to drive the crystal. |
| 4 | XIN/REF | input | Crystal oscillator interface input, or single-ended LVCMOS clock input; the input voltage must be 1.2V max (see Overdriving the XIN/REF Interface). |
| 5 | VDDA | power_in | Analog functions power supply, connect to 1.8V to 3.3V; VDDA and VDDD must have the same voltage applied. |
| 6 | CLKSEL | input | Input clock select for manual switchover: 0 = XIN/REF, XOUT (default), 1 = CLKIN, CLKINB; internal pull-down. |
| 7 | SD/OE | input | Configurable as global shutdown (SD) or output enable (OE) via the SH bit; when used as OE the default polarity is active LOW, and it has a weak internal pull-down. |
| 8 | SEL1/SDA | bidirectional | Configuration select input SEL1, or I2C SDA when OUT0_SEL_I2CB is low at power-up; weak internal pull-down. |
| 9 | SEL0/SCL | bidirectional | Configuration select input SEL0, or I2C SCL when OUT0_SEL_I2CB is low at power-up; weak internal pull-down. |
| 10 | VDDA | power_in | Analog functions power supply, connect to 1.8V to 3.3V; VDDA and VDDD must have the same voltage applied. |
| 11 | NC | unconnected | No connect. |
| 12 | NC | unconnected | No connect. |
| 13 | NC | unconnected | No connect. |
| 14 | NC | unconnected | No connect. |
| 15 | VDDA | power_in | Analog functions power supply, connect to 1.8V to 3.3V; VDDA and VDDD must have the same voltage applied. |
| 16 | NC | unconnected | No connect. |
| 17 | OUT2 | output | Output clock 2 (LVCMOS); output voltage set by VDDO2 at 1.8V, 2.5V or 3.3V. |
| 18 | VDDO2 | power_in | Output power supply, connect to 1.8V to 3.3V; sets the output voltage level for OUT2. |
| 19 | NC | unconnected | No connect. |
| 20 | OUT1 | output | Output clock 1 (LVCMOS); output voltage set by VDDO1 at 1.8V, 2.5V or 3.3V. |
| 21 | VDDO1 | power_in | Output power supply, connect to 1.8V to 3.3V; sets the output voltage level for OUT1. |
| 22 | VDDD | power_in | Digital functions power supply, connect to 1.8V to 3.3V; VDDA and VDDD must have the same voltage applied. |
| 23 | VDDO0 | power_in | Output power supply for OUT0_SEL_I2CB, connect to 1.8V to 3.3V; sets the output voltage level for OUT0. |
| 24 | OUT0_SEL_I2CB | bidirectional | Latched at power-up to select the function of pins 8 and 9 (pull-up: SEL1/SEL0 hardware select; pull-down or float: SDA/SCL I2C), then acts as an LVCMOS reference output; internal pull-down. |
| 25 | GND | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | RENESAS |
| Package | QFN-24(4x4) |
| Category | Clock and Timing |
| Pins | 25 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input HIGH level (SEL1/SDA, SEL0/SCL) | VIH | 5.5 | V | For SEL1/SDA pin and SEL0/SCL pin | 11 | ||
| Output LOW voltage | VOL | 0.4 | V | IOL = 3 mA | 11 | ||
| Input leakage current | IIN | -1 | 30 | µA | 11 | ||
| Serial clock frequency (SCL) | FSCLK | 10 | 400 | kHz | 11 | ||
| Bus free time between STOP and START | tBUF | 1.3 | µs | 11 | |||
| Setup time, START | tSU:START | 0.6 | µs | 11 | |||
| Hold time, START | tHD:START | 0.6 | µs | 11 | |||
| Setup time, data input (SDA) | tSU:DATA | 0.1 | µs | 11 | |||
| Hold time, data input (SDA) | tHD:DATA | 0 | µs | 11 | |||
| Output data valid from clock | tOVD | 0.9 | µs | 11 | |||
| Capacitive load for each bus line | CB | 400 | pF | 11 | |||
| Rise time, data and clock (SDA, SCL) | tR | 300 | ns | min = 20 + 0.1xCB | 11 | ||
| Fall time, data and clock (SDA, SCL) | tF | 300 | ns | min = 20 + 0.1xCB | 11 | ||
| HIGH time, clock (SCL) | tHIGH | 0.6 | µs | 11 | |||
| LOW time, clock (SCL) | tLOW | 1.3 | µs | 11 | |||
| Setup time, STOP | tSU:STOP | 0.6 | µs | 11 | |||
| Supply voltage VDDA, VDDD, VDDO | VDDA, VDDD, VDDO | 3.465 | V | 12 | |||
| XIN/REF input voltage swing | 0 | 1.2 | V | 0V to 1.2V voltage swing | 12 | ||
| CLKIN, CLKINB input voltage swing | 0 | 1.2 | V | 0V to 1.2V voltage swing single-ended | 12 | ||
| Other inputs voltage | -0.5 | V | 12 | ||||
| Outputs VDDO (LVCMOS) voltage | VDDO | -0.5 | V | 12 | |||
| Outputs IO (SDA) current | IO | 10 | mA | 12 | |||
| Storage temperature | TSTG | -65 | 150 | C | 12 | ||
| ESD Human Body Model | 2000 | V | Human Body Model | 12 | |||
| Junction temperature | 125 | °C | 12 | ||||
| Power supply voltage for supporting 1.8V outputs | VDDOX | 1.71 | 1.8 | 1.89 | V | Power supply voltage for supporting 1.8V outputs | 12 |
| Power supply voltage for supporting 2.5V outputs | VDDOX | 2.375 | 2.5 | 2.625 | V | Power supply voltage for supporting 2.5V outputs | 12 |
| Power supply voltage for supporting 3.3V outputs | VDDOX | 3.135 | 3.3 | 3.465 | V | Power supply voltage for supporting 3.3V outputs | 12 |
| Power supply voltage for core logic functions | VDDD | 1.71 | 3.465 | V | 12 | ||
| Analog power supply voltage | VDDA | 1.71 | 3.465 | V | Use filtered analog power supply | 12 | |
| Operating temperature, ambient | TA | -40 | 85 | °C | 12 | ||
| Maximum load capacitance | CLOAD_OUT | 15 | pF | 3.3V LVCMOS only | 12 | ||
| External reference crystal frequency | FIN | 1 | 40 | MHz | External reference crystal | 12 | |
| External reference clock CLKIN, CLKINB frequency | 1 | 200 | MHz | External reference clock CLKIN, CLKINB | 12 | ||
| Power up time for all VDDs to minimum specified voltage | tPU | 0.05 | 5 | ms | Power ramps must be monotonic | 12 | |
| Package thermal impedance, junction to ambient | JA | 42 | C/W | 0 mps | 12 | ||
| Package thermal impedance, junction to case | JC | 41.8 | C/W | 0 mps | 12 | ||
| Input capacitance (CLKIN, CLKINB, CLKSEL, SD/OE, SEL1/SDA, SEL0/SCL) | CIN | 3 | 7 | pF | TA = +25 °C | 13 | |
| Pull-down resistor (CLKSEL, SD/OE, SEL1/SDA, SEL0/SCL, CLKIN, CLKINB, OUT0_SEL_I2CB) | 100 | 300 | k | TA = +25 °C | 13 | ||
| LVCMOS output driver impedance | ROUT | 17 | VDDO = 1.8V, 2.5V, 3.3V | 13 | |||
| Programmable input capacitance at XIN/REF | 0 | 8 | pF | TA = +25 °C | 13 | ||
| Programmable input capacitance at XOUT | 0 | 8 | pF | TA = +25 °C | 13 | ||
| Core supply current | Iddcore3 | 30 | 34 | mA | 100 MHz on all outputs, 25 MHz REFCLK | 13 | |
| Output buffer supply current, 50 MHz, 3.3V VDDOX | Iddox | 16 | 18 | mA | LVCMOS, 50 MHz, 3.3V VDDOX | 13 | |
| Output buffer supply current, 200 MHz, 3.3V VDDOX | Iddox | 36 | 42 | mA | LVCMOS, 200 MHz, 3.3V VDDOX | 13 | |
| Core power down current | Iddpd | 10 | 14 | mA | SD asserted, I2C Programming | 13 | |
| Output HIGH voltage | VOH | 2.4 | V | IOH = -15mA | 14 | ||
| Output LOW voltage | VOL | 0.4 | V | IOL = 15mA | 14 | ||
| Input HIGH voltage, CLKIN/CLKINB | VIH | 0.55 | 1.7 | V | Single-ended input | 14 | |
| Input LOW voltage, CLKIN/CLKINB | VIL | 0.4 | V | Single-ended input | 14 | ||
| Input amplitude, CLKIN/CLKINB | VSWING | 200 | 1200 | mV | Peak to peak value, single-ended | 14 | |
| Input slew rate, CLKIN/CLKINB | dv/dt | 0.4 | 8 | V/ns | Measured differentially | 14 | |
| Input leakage low current, CLKIN/CLKINB | IIL | -5 | 5 | µA | VIN = GND | 14 | |
| Input duty cycle | dTIN | 45 | 55 | % | Measurement from differential waveform | 14 | |
| Output leakage current (OUT1~2) | IOZDD | 5 | µA | Tri-state outputs, VDDO = 3.465V | 14 | ||
| Input frequency limit (XIN) | fIN | 8 | 40 | MHz | Input frequency limit (XIN) | 16 | |
| Single ended clock output frequency limit (LVCMOS) | fOUT | 1 | 200 | MHz | Single ended clock output limit (LVCMOS) | 16 | |
| VCO operating frequency range | fVCO | 2600 | 2900 | MHz | VCO operating frequency range | 16 | |
| PFD operating frequency range | fPFD | 11 | 150 | MHz | PFD operating frequency range | 16 | |
| Output duty cycle, outputs except OUT0 | t3 | 45 | 50 | 55 | % | Measured at VDD/2, all outputs except OUT0, VDDOX = 2.5V or 3.3V | 16 |
CAD (KiCad official)
- Symbol:
5P49V5923B000NLGI - Footprint:
Package_DFN_QFN:QFN-24-1EP_4x4mm_P0.5mm_EP2.6x2.6mm - 3D model: QFN-24(4x4) (KiCad packages3D, STEP)
- 3D model files:
5p49v5923b000nlgi-etched.step/5p49v5923b000nlgi-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);5p49v5923b000nlgi.step/5p49v5923b000nlgi.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: RENESAS datasheet (28 pp, sha256
d73d04035617efba, retrieved 2026-10-30, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).