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557G-03LFT

Public Made by Adom

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RENESAS Clock Generators / Frequency Synthesizers / PLL, TSSOP-16-175mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentclock and timing557g-03lftfactory-2.0.0extractor-text

Verified 557G-03LFT

by Ray · last 30 Oct 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

30 Oct 2026RayPublished by the parts factory: tier lcsc, 16 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: 557G-03LFT · TSSOP-16-175mil · 16 pins
  • ✓copper: 16 copper pads, none touching another net
  • ✓datasheet: all 16 pin names found in the 12-page datasheet
  • ✓distributor: lcsc C2651403, digikey 6690-557G-03LFTTR-ND, mouser 972-557G-03LFT
  • ✓family: TSSOP-16_4.4x5mm_P0.65mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-ohvkiydz/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • ✓package_fit: height and body within the datasheet's package drawing (datasheet p.10)
  • ✓pads: 16 pins = 16 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 16 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ 557g-03lft.kicad_sym✓ 557g-03lft.kicad_mod✓ 557g-03lft.step
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Contents

README

markdown

557G-03LFT

RENESAS · Clock Generators / Frequency Synthesizers / PLL · TSSOP-16-175mil

557G-03LFT from RENESAS, in a TSSOP-16-175mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 S0 input Select pin 0 sets the output frequency together with S1 per Table 1 (25M, 100M, 125M or 200M) and has an internal pull-up resistor.
2 S1 input Select pin 1 sets the output frequency together with S0 per Table 1 and has an internal pull-up resistor.
3 SS0 input Spread select pin 0 sets the spread type and amount together with SS1 per Table 2 and has an internal pull-up resistor.
4 X1/ICLK input Crystal or clock input, to be connected to a 25 MHz crystal or a single-ended clock.
5 X2 output Crystal connection, to be left unconnected when a clock is applied to X1/ICLK.
6 OE input Output enable; a low level tri-states the outputs without shutting the device down, and it has an internal pull-up resistor.
7 GNDXD power_in Connect to ground.
8 SS1 input Spread select pin 1 sets the spread type and amount together with SS0 per Table 2 and has an internal pull-up resistor.
9 IREF output Precision reference resistor pin connected to the internal current reference; RR = 475 Ω (1%) gives IREF of 2.32 mA for a 50 Ω board trace.
10 CLK1 output HCSL complementary clock output 1.
11 CLK1 output HCSL true clock output 1.
12 VDDODA power_in Connect to a +3.3 V supply for the output driver and analog circuits.
13 GNDODA power_in Connect to ground.
14 CLK0 output HCSL complementary clock output 0.
15 CLK0 output HCSL true clock output 0.
16 VDDXD power_in Connect to a +3.3 V supply for the crystal oscillator and digital circuits.

Key specifications

Parameter Value
Manufacturer RENESAS
Package TSSOP-16-175mil
Category Clock and Timing
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage V 2.97 3.3 3.63 V 6
Ambient operating temperature (commercial) 0 70 °C 6
Supply voltage (absolute maximum), VDDXD, VDDODA VDDXD, VDDODA 7 V 6
All inputs and outputs -0.5 V Max printed as VDD+0.5 V 6
Storage temperature -65 150 °C 6
Junction temperature 125 °C 6
Soldering temperature 260 °C 6
ESD protection (input) 2000 V HBM 6
Input high voltage VIH 2 V S0, S1, OE, ICLK, SS0, SS1; max printed as VDD+0.3 6
Input low voltage VIL 0.8 V S0, S1, OE, ICLK, SS0, SS1; min printed as VSS-0.3 6
Input leakage current IIL -5 5 μA 0 < Vin < VDD 6
Output high voltage VOH 660 700 850 mV 7
Output low voltage VOL -150 0 27 mV 7
Crossing point voltage (absolute) 250 350 550 mV Absolute 7
Rise time tOR 175 332 700 ps From 0.175 V to 0.525 V 7
Fall time tOF 175 344 700 ps From 0.525 V to 0.175 V 7
Modulation frequency 30 31.5 33 kHz Spread spectrum 7
Jitter, phase (PCIe Gen 1) tjphasePLL 86 ps (p-p) PCIe Gen 1 8

CAD (KiCad official)

  • Symbol: 557G-03LFT
  • Footprint: Package_SO:TSSOP-16_4.4x5mm_P0.65mm
  • 3D model: TSSOP-16-175mil (KiCad packages3D, STEP)
  • 3D model files: 557g-03lft-etched.step / 557g-03lft-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); 557g-03lft.step / 557g-03lft.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: RENESAS datasheet (12 pp, sha256 72c78dc62d05844e, retrieved 2026-10-30, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF