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Generated by kicad-footprint-generator · KiCad file format 20260206

Name	Last commit message	Last updated
docs	Publish 0.1.0 · Ray	2d ago
viewers	551mlft: viewers · Ray	2d ago
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551mlft-etched.step	551mlft: factory component page (tier=lcsc) · Ray	2d ago
551mlft-hero.glb	551mlft: hero GLB from the etched model (keeps the MPN mark) · Ray	2d ago
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README.md	Publish 0.1.0 · Ray	2d ago

551MLFT

RENESAS · Clock Buffers, Drivers · SOIC-8

551MLFT from RENESAS, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	ICLK	input	Clock input with an internal pull-up resistor; the datasheet gives VIH/VIL thresholds at VDD/2 ±0.7 V for 3.3 V operation and VDD/2 ±1 V for 5 V operation.
2	Q1	output	Non-inverting clock output 1, with output-to-output skew of 250 ps maximum between outputs under equal loading.
3	Q2	output	Non-inverting clock output 2, with output-to-output skew of 250 ps maximum between outputs under equal loading.
4	Q3	output	Non-inverting clock output 3, with output-to-output skew of 250 ps maximum between outputs under equal loading.
5	Q4	output	Non-inverting clock output 4, with output-to-output skew of 250 ps maximum between outputs under equal loading.
6	GND	power_in	Ground connection; the datasheet recommends a 0.01 µF decoupling capacitor between VDD (pin 7) and this pin, placed as close to the device as possible.
7	VDD	power_in	Supply pin to be connected to 3.3 V or 5.0 V; operating range is 3.0 to 3.6 V at 3.3 V and 4.5 to 5.5 V at 5 V, with absolute maximum 7 V.
8	OE	input	Output enable input with internal pull-up resistor that tri-states all clock outputs when driven low; VIH is 2 V minimum and VIL is 0.8 V maximum.

Key specifications

Parameter	Value
Manufacturer	RENESAS
Package	SOIC-8
Category	Clock and Timing
Pins	8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Supply Voltage, VDD	VDD			7	V		3
All Inputs and Outputs		-0.5			V		3
Ambient Operating Temperature, Commercial		0		70	°C	Commercial grade (551MLF / 551MLFT)	3
Power Supply Voltage (measured in respect to GND)		3		5.5	V	Measured with respect to GND	3
Storage Temperature		-65		150	°C		3
Junction Temperature				125	°C		3
Soldering Temperature				260	°C		3
Operating Voltage	VDD	3		3.6	V	Table VDD=3.3 V ±10%, ambient -40 to +85 °C	4
Input High Voltage, ICLK	VIH			3.8	V	Table VDD=3.3 V ±10%, ambient -40 to +85 °C; Note 1 (nominal switching threshold VDD/2)	4
Input High Voltage, OE	VIH	2			V	Table VDD=3.3 V ±10%, ambient -40 to +85 °C	4
Input Low Voltage, OE	VIL			0.8	V	Table VDD=3.3 V ±10%, ambient -40 to +85 °C	4
Output High Voltage	VOH	2.4			V	Table VDD=3.3 V ±10%, ambient -40 to +85 °C; IOH = -25 mA	4
Output Low Voltage	VOL			0.4	V	Table VDD=3.3 V ±10%, ambient -40 to +85 °C; IOL = 25 mA	4
Operating Supply Current	IDD			18	mA	Table VDD=3.3 V ±10%, ambient -40 to +85 °C; no load, 135 MHz	4
Short Circuit Current	IOS	-50		50	mA	Table VDD=3.3 V ±10%, ambient -40 to +85 °C	4
Operating Voltage	VDD	4.5		5.5	V	Table VDD=5 V ±10%, ambient -40 to +85 °C	4
Input High Voltage, ICLK	VIH			5.5	V	Table VDD=5 V ±10%, ambient -40 to +85 °C; Note 1 (nominal switching threshold VDD/2)	4
Operating Supply Current	IDD			35	mA	Table VDD=5 V ±10%, ambient -40 to +85 °C; no load, 135 MHz	4
Short Circuit Current	IOS	-80		80	mA	Table VDD=5 V ±10%, ambient -40 to +85 °C	4
Input Frequency		0		160	MHz	Table VDD=3.3 V ±10%, ambient -40 to +85 °C	5
Output Frequency				160	MHz	Table VDD=3.3 V ±10%, ambient -40 to +85 °C; 15 pF load, Note 4	5
Output Clock Rise Time	tOR			1	ns	Table VDD=3.3 V ±10%, ambient -40 to +85 °C; 0.8 to 2.0 V	5
Output Clock Fall Time	tOF			1	ns	Table VDD=3.3 V ±10%, ambient -40 to +85 °C; 2.0 to 0.8 V	5
Propagation Delay		2	4	8	ns	Table VDD=3.3 V ±10%, ambient -40 to +85 °C; Note 1, 135 MHz	5
Output to Output Skew				250	ps	Table VDD=3.3 V ±10%, ambient -40 to +85 °C; Note 2, rising edges at VDD/2	5
Input Frequency		0		135	MHz	Table VDD=5 V ±10%, ambient -40 to +85 °C	5
Output Frequency				135	MHz	Table VDD=5 V ±10%, ambient -40 to +85 °C; 15 pF load, Note 4	5
Propagation Delay		1.5	3	6	ns	Table VDD=5 V ±10%, ambient -40 to +85 °C; Note 1, 135 MHz	5
Nominal Output Impedance	ZO		20		Ω	Table VDD=3.3 V ±10%, ambient -40 to +85 °C	4
Internal Pull-up Resistor	RPU		500		kΩ	Table VDD=3.3 V ±10%, ambient -40 to +85 °C; OE pin	4
Input Capacitance	CIN		5		pF	Table VDD=3.3 V ±10%, ambient -40 to +85 °C; OE pin	4
Internal Pull-up Resistor	RPU		220		kΩ	Table VDD=5 V ±10%, ambient -40 to +85 °C; OE pin	4

CAD (KiCad official)

Symbol: 551MLFT
Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
3D model: SOIC-8 (KiCad packages3D, STEP)
3D model files: 551mlft-etched.step / 551mlft-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); 551mlft.step / 551mlft.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: RENESAS datasheet (10 pp, sha256 802e91a02e0502bd, retrieved 2026-10-29, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF