component
501MLF
Public Made by Adomby adom
RENESAS Clock Generators / Frequency Synthesizers / PLL, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
main
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"title": "501MLF",
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"package": "SOIC-8",
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"category": "Clock And Timing",
"subcategory": "Clock Generators / Frequency Synthesizers / PLL",
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"digikey": "6690-501MLF-ND",
"mouser": "972-501MLF"
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"source": "Component Ocean /api/assign-pns",
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"description": "Crystal connection or clock input, specified for a 5 to 27 MHz crystal input or a 2 to 50 MHz clock input."
},
{
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"name": "VDD",
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"description": "Supply pin, connected to +3.3 V or +5 V, with an operating range of 3.0 V to 5.25 V."
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{
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"description": "Ground connection; a 0.01 µF decoupling capacitor must be connected between VDD and GND close to the device."
},
{
"number": "4",
"name": "S1",
"type": "input",
"description": "Tri-level select input for the output clock multiplier; connect to GND, to VDD, or leave floating."
},
{
"number": "5",
"name": "CLK",
"type": "output",
"description": "Clock output at the frequency set by the S1/S0 selection table, with output frequency up to 160 MHz at VDD 4.75 to 5.25 V and duty cycle of 45/55 up to 160 MHz."
},
{
"number": "6",
"name": "S0",
"type": "input",
"description": "Tri-level select input for the output clock multiplier; connect to GND, to VDD, or leave floating."
},
{
"number": "7",
"name": "OE",
"type": "input",
"description": "Output enable that tri-states the CLK output when taken low, with VIH of 2.0 V minimum, VIL of 0.8 V maximum, and an internal 270 kΩ pull-up."
},
{
"number": "8",
"name": "X2",
"type": "output",
"description": "Crystal connection; leave unconnected when pin 1 is driven as a clock input."
}
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{
"name": "Output Clock Rise Time",
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{
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{
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{
"name": "Output Disable Time, OE low to tri-state",
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{
"name": "Absolute Clock Period Jitter",
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"min": null,
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"conditions": "Deviation from mean",
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{
"name": "One Sigma Clock Period Jitter",
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"min": null,
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"name": "Thermal Resistance Junction to Ambient (8SOIC)",
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{
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{
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{
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