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501MLF

Public Made by Adom

by adom

RENESAS Clock Generators / Frequency Synthesizers / PLL, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentclock and timing501mlffactory-2.0.0extractor-text

Verified 501MLF

by Ray · last 31 Oct 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

31 Oct 2026RayPublished by the parts factory: tier lcsc, 8 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: 501MLF · SOIC-8 · 8 pins
  • ✓copper: 8 copper pads, none touching another net
  • ✓datasheet: all 8 pin names found in the 10-page datasheet
  • ✓distributor: lcsc C6071508, digikey 6690-501MLF-ND, mouser 972-501MLF
  • ✓family: SOIC-8_3.9x4.9mm_P1.27mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-9sydt5xe/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • ✓package_fit: height and body within the datasheet's package drawing (datasheet p.7)
  • ✓pads: 8 pins = 8 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 8 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ 501mlf.kicad_sym✓ 501mlf.kicad_mod✓ 501mlf.step
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Ray Publish 0.1.0 74d5e5d 2d ago

501MLF

RENESAS · Clock Generators / Frequency Synthesizers / PLL · SOIC-8

501MLF from RENESAS, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 X1/ICLK input Crystal connection or clock input, specified for a 5 to 27 MHz crystal input or a 2 to 50 MHz clock input.
2 VDD power_in Supply pin, connected to +3.3 V or +5 V, with an operating range of 3.0 V to 5.25 V.
3 GND power_in Ground connection; a 0.01 µF decoupling capacitor must be connected between VDD and GND close to the device.
4 S1 input Tri-level select input for the output clock multiplier; connect to GND, to VDD, or leave floating.
5 CLK output Clock output at the frequency set by the S1/S0 selection table, with output frequency up to 160 MHz at VDD 4.75 to 5.25 V and duty cycle of 45/55 up to 160 MHz.
6 S0 input Tri-level select input for the output clock multiplier; connect to GND, to VDD, or leave floating.
7 OE input Output enable that tri-states the CLK output when taken low, with VIH of 2.0 V minimum, VIL of 0.8 V maximum, and an internal 270 kΩ pull-up.
8 X2 output Crystal connection; leave unconnected when pin 1 is driven as a clock input.

Key specifications

Parameter Value
Manufacturer RENESAS
Package SOIC-8
Category Clock And Timing
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Power Supply Voltage (measured in respect to GND) 3 5.25 V 3
Ambient Operating Temperature (commercial) 0 70 C 3
Supply Voltage, VDD VDD 7 V 3
All Inputs and Outputs (upper limit VDD+0.5 V, not converted) -0.5 V 3
Ambient Operating Temperature (absolute maximum rating) -40 85 C 3
Storage Temperature -65 150 C 3
Soldering Temperature 260 C 3
Operating Voltage VDD 3 5.25 V 4
Input High Voltage VIH, OE (pin 7) VIH 2 V OE (pin 7) 4
Input Low Voltage VIL, OE (pin 7) VIL 0.8 V OE (pin 7) 4
Input Low Voltage VIL, S0, S1 VIL 0.5 V S0, S1 4
Output High Voltage VOH 2.4 V IOH = -25 mA 4
Output Low Voltage VOL 0.4 V IOL = 25 mA 4
IDD Operating Supply Current IDD 20 mA No load, 100M 4
Short Circuit Current 70 mA CLK output 4
Input Frequency, clock input FIN 2 50 MHz clock input 5
Output Frequency (commercial, 0C to +70C) FOUT 13 160 MHz VDD = 4.75 to 5.25 V, 0C to +70C 5
Output Frequency (commercial, 0C to +70C) FOUT 13 100 MHz VDD = 3.0 to 3.6 V, 0C to +70C 5
Output Clock Rise Time tOR 1 ns 0.8 to 2.0 V, Note 1 5
Output Clock Fall Time tOF 1 ns 2.0 to 8.0 V, Note 1 5
Output Clock Duty Cycle tOD 45 55 % 1.5 V, up to 160 MHz 5
Output Enable Time, OE high to output on 50 ns OE high to output on 5
Output Disable Time, OE low to tri-state 50 ns OE low to tri-state 5
Absolute Clock Period Jitter tja 70 ps Deviation from mean 5
One Sigma Clock Period Jitter tjs 25 ps 5
Thermal Resistance Junction to Ambient (8SOIC) JA 150 C/W Still air 5
Thermal Resistance Junction to Ambient (8SOIC) JA 140 C/W 1 m/s air flow 5
Thermal Resistance Junction to Ambient (8SOIC) JA 120 C/W 3 m/s air flow 5
Thermal Resistance Junction to Case (8SOIC) JC 40 C/W 5
Thermal Resistance Junction to Top of Case (8SOIC) JT 20 C/W Still air 5

CAD (KiCad official)

  • Symbol: 501MLF
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOIC-8 (KiCad packages3D, STEP)
  • 3D model files: 501mlf-etched.step / 501mlf-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); 501mlf.step / 501mlf.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: RENESAS datasheet (10 pp, sha256 32d23f770fe5a33d, retrieved 2026-10-31, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF