component
501MILFT
Public Made by Adomby adom
RENESAS Clock Generators, PLLs, Frequency Synthesizers, SOIC-8. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.
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page.json+158−8@@ -1,13 +1,168 @@ {+ "schema_version": 1,+ "type": "component", "slug": "501milft",+ "title": "501MILFT",+ "brief": "RENESAS Clock Generators, PLLs, Frequency Synthesizers, SOIC-8. Datasheet-verified pinout, KiCad symbol/footprint/3D.", "version": "0.1.0",- "type": "component",- "description": "RENESAS Clock Generators, PLLs, Frequency Synthesizers, SOIC-8. Datasheet-verified pinout, KiCad symbol/footprint/3D.",+ "license": "CC-BY-SA-4.0", "tags": [ "component", "clock-timing", "501milft" ],+ "component": {+ "mpn": "501MILFT",+ "manufacturer": "RENESAS",+ "package": "SOIC-8",+ "pin_count": 8,+ "category": "Clock/Timing",+ "subcategory": "Clock Generators, PLLs, Frequency Synthesizers",+ "datasheet": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588953769791275008",+ "parts": {+ "symbol": "501milft.kicad_sym",+ "footprint": "501milft.kicad_mod",+ "model_3d": "501milft.glb",+ "model_3d_step": "501milft.step",+ "lbr": "501milft.lbr"+ },+ "distributor_links": {},+ "pins": [+ {+ "number": "1",+ "name": "X1/ICLK",+ "type": "input",+ "description": "Crystal connection (X1) or external clock input (ICLK). Accepts a fundamental-mode parallel-resonant crystal (5-27 MHz) or a CMOS/TTL clock input (2-50 MHz). VIH = (VDD/2)+1 V, VIL = (VDD/2)-1 V when driven as ICLK."+ },+ {+ "number": "2",+ "name": "VDD",+ "type": "power_in",+ "description": "Positive supply. Connect to +3.3 V or +5 V (operating range +3.0 V to +5.25 V). Requires a 0.01 \u00b5F decoupling capacitor to GND placed close to the pin."+ },+ {+ "number": "3",+ "name": "GND",+ "type": "power_in",+ "description": "Ground reference. Connect to system ground."+ },+ {+ "number": "4",+ "name": "S1",+ "type": "input",+ "description": "Tri-level select input (bit 1) for the PLL multiplication factor. Connect directly to GND (0), directly to VDD (1), or leave floating (M) to choose one of nine multiplication ratios per the Clock Output Table. VIH = VDD-0.5 V, VIL = 0.5 V."+ },+ {+ "number": "5",+ "name": "CLK",+ "type": "tri_state",+ "description": "PLL clock output. Frequency = input \u00d7 selected multiplier (up to 160 MHz at 5 V, up to 100 MHz at 3.3 V). 25 mA drive at TTL levels (VOH \u2265 2.4 V at -25 mA, VOL \u2264 0.4 V at 25 mA). ~20 \u03a9 nominal output impedance; recommend a 33 \u03a9 series termination for traces > 1 inch. Tri-stated when OE is low."+ },+ {+ "number": "6",+ "name": "S0",+ "type": "input",+ "description": "Tri-level select input (bit 0) for the PLL multiplication factor. Connect directly to GND (0), directly to VDD (1), or leave floating (M). Combined with S1 to select one of nine multiplication ratios. VIH = VDD-0.5 V, VIL = 0.5 V."+ },+ {+ "number": "7",+ "name": "OE",+ "type": "input",+ "description": "Output Enable. Active-high: CLK is enabled when OE is high and tri-stated when OE is low. Contains an internal 270 k\u03a9 pull-up to VDD so the pin defaults enabled if left open. VIH = 2.0 V, VIL = 0.8 V; enable/disable time ~50 ns."+ },+ {+ "number": "8",+ "name": "X2",+ "type": "output",+ "description": "Crystal connection (oscillator feedback pin). Connect to the second terminal of the fundamental-mode crystal. Leave unconnected when driving X1/ICLK with an external clock. On-chip capacitance is ~12 pF; add external load caps to X1 and X2 to match crystal CL (each cap = (CL - 12) \u00d7 2 pF)."+ }+ ],+ "provenance": {+ "extractor": "ds2sf",+ "datasheet": {+ "url": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588953769791275008",+ "pages": 10,+ "sha256": "a6b6a688d3d2902a",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 8,+ "described": 8,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ }+ },+ "metadata": {+ "specs": {+ "Manufacturer": "RENESAS",+ "Package": "SOIC-8",+ "Category": "Clock/Timing",+ "Pins": "8"+ }+ },+ "variants": [+ {+ "mpn": "501MLF",+ "kind": "unknown"+ },+ {+ "mpn": "501MLFT",+ "kind": "unknown"+ },+ {+ "mpn": "501MILFT",+ "kind": "packaging"+ },+ {+ "mpn": "501MILFT501GLF",+ "kind": "packaging"+ },+ {+ "mpn": "501MILFT501GLFT",+ "kind": "packaging"+ },+ {+ "mpn": "501MILFT501GILF",+ "kind": "packaging"+ },+ {+ "mpn": "501MILFT501GILFT",+ "kind": "packaging"+ },+ {+ "mpn": "501MILFT501-DWF",+ "kind": "packaging"+ },+ {+ "mpn": "501MILFT501-DPK",+ "kind": "packaging"+ },+ {+ "mpn": "501MILFT501E-DPK",+ "kind": "packaging"+ }+ ],+ "sections": [+ "hero",+ "viewers",+ "readme",+ "breadcrumbs",+ "info"+ ],+ "discovery_triggers": [+ "501milft"+ ],+ "discovery_pitch": "501MILFT (RENESAS) component page with datasheet-verified CAD.",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }, "dependencies": {}, "hero": { "type": "image",@@ -25,10 +180,5 @@ "docs/501milft-datasheet.pdf", "viewers/symbol.html", "viewers/footprint.html"- ],- "visibility": "public",- "author": {- "name": "Ray",- "email": "[email protected]"- }+ ] }