501MILFT

@@ -0,0 +1,58 @@+# 501MILFT++**RENESAS** · Clock Generators, PLLs, Frequency Synthesizers · SOIC-8++501MILFT from RENESAS, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | X1/ICLK | input | Crystal connection (X1) or external clock input (ICLK). Accepts a fundamental-mode parallel-resonant crystal (5-27 MHz) or a CMOS/TTL clock input (2-50 MHz). VIH = (VDD/2)+1 V, VIL = (VDD/2)-1 V when driven as ICLK. |+| 2 | VDD | power_in | Positive supply. Connect to +3.3 V or +5 V (operating range +3.0 V to +5.25 V). Requires a 0.01 µF decoupling capacitor to GND placed close to the pin. |+| 3 | GND | power_in | Ground reference. Connect to system ground. |+| 4 | S1 | input | Tri-level select input (bit 1) for the PLL multiplication factor. Connect directly to GND (0), directly to VDD (1), or leave floating (M) to choose one of nine multiplication ratios per the Clock Output Table. VIH = VDD-0.5 V, VIL = 0.5 V. |+| 5 | CLK | tri_state | PLL clock output. Frequency = input × selected multiplier (up to 160 MHz at 5 V, up to 100 MHz at 3.3 V). 25 mA drive at TTL levels (VOH ≥ 2.4 V at -25 mA, VOL ≤ 0.4 V at 25 mA). ~20 Ω nominal output impedance; recommend a 33 Ω series termination for traces > 1 inch. Tri-stated when OE is low. |+| 6 | S0 | input | Tri-level select input (bit 0) for the PLL multiplication factor. Connect directly to GND (0), directly to VDD (1), or leave floating (M). Combined with S1 to select one of nine multiplication ratios. VIH = VDD-0.5 V, VIL = 0.5 V. |+| 7 | OE | input | Output Enable. Active-high: CLK is enabled when OE is high and tri-stated when OE is low. Contains an internal 270 kΩ pull-up to VDD so the pin defaults enabled if left open. VIH = 2.0 V, VIL = 0.8 V; enable/disable time ~50 ns. |+| 8 | X2 | output | Crystal connection (oscillator feedback pin). Connect to the second terminal of the fundamental-mode crystal. Leave unconnected when driving X1/ICLK with an external clock. On-chip capacitance is ~12 pF; add external load caps to X1 and X2 to match crystal CL (each cap = (CL - 12) × 2 pF). |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | RENESAS |+| Package | SOIC-8 |+| Category | Clock/Timing |+| Pins | 8 |++## Ordering variants++Same part, different packaging or reel option.++- `501MLF`+- `501MLFT`+- `501MILFT`+- `501MILFT501GLF`+- `501MILFT501GLFT`+- `501MILFT501GILF`+- `501MILFT501GILFT`+- `501MILFT501-DWF`+- `501MILFT501-DPK`+- `501MILFT501E-DPK`++## CAD (KiCad official)++- Symbol: `501MILFT`+- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`+- 3D model: SOIC-8 (KiCad packages3D, STEP)++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [RENESAS datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588953769791275008) (10 pp, sha256 `a6b6a688d3d2902a`, retrieved 2026-08-17, tier: lcsc)+- **Extractor:** `ds2sf` (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/501milft-datasheet.pdf)

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