component
501MILFT
Public Made by Adomby adom
RENESAS Clock Generators, PLLs, Frequency Synthesizers, SOIC-8. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.
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page.json+8−5@@ -38,7 +38,7 @@ "number": "2", "name": "VDD", "type": "power_in",- "description": "Positive supply. Connect to +3.3 V or +5 V (operating range +3.0 V to +5.25 V). Requires a 0.01 \u00b5F decoupling capacitor to GND placed close to the pin."+ "description": "Positive supply. Connect to +3.3 V or +5 V (operating range +3.0 V to +5.25 V). Requires a 0.01 µF decoupling capacitor to GND placed close to the pin." }, { "number": "3",@@ -56,7 +56,7 @@ "number": "5", "name": "CLK", "type": "tri_state",- "description": "PLL clock output. Frequency = input \u00d7 selected multiplier (up to 160 MHz at 5 V, up to 100 MHz at 3.3 V). 25 mA drive at TTL levels (VOH \u2265 2.4 V at -25 mA, VOL \u2264 0.4 V at 25 mA). ~20 \u03a9 nominal output impedance; recommend a 33 \u03a9 series termination for traces > 1 inch. Tri-stated when OE is low."+ "description": "PLL clock output. Frequency = input × selected multiplier (up to 160 MHz at 5 V, up to 100 MHz at 3.3 V). 25 mA drive at TTL levels (VOH ≥ 2.4 V at -25 mA, VOL ≤ 0.4 V at 25 mA). ~20 Ω nominal output impedance; recommend a 33 Ω series termination for traces > 1 inch. Tri-stated when OE is low." }, { "number": "6",@@ -68,13 +68,13 @@ "number": "7", "name": "OE", "type": "input",- "description": "Output Enable. Active-high: CLK is enabled when OE is high and tri-stated when OE is low. Contains an internal 270 k\u03a9 pull-up to VDD so the pin defaults enabled if left open. VIH = 2.0 V, VIL = 0.8 V; enable/disable time ~50 ns."+ "description": "Output Enable. Active-high: CLK is enabled when OE is high and tri-stated when OE is low. Contains an internal 270 kΩ pull-up to VDD so the pin defaults enabled if left open. VIH = 2.0 V, VIL = 0.8 V; enable/disable time ~50 ns." }, { "number": "8", "name": "X2", "type": "output",- "description": "Crystal connection (oscillator feedback pin). Connect to the second terminal of the fundamental-mode crystal. Leave unconnected when driving X1/ICLK with an external clock. On-chip capacitance is ~12 pF; add external load caps to X1 and X2 to match crystal CL (each cap = (CL - 12) \u00d7 2 pF)."+ "description": "Crystal connection (oscillator feedback pin). Connect to the second terminal of the fundamental-mode crystal. Leave unconnected when driving X1/ICLK with an external clock. On-chip capacitance is ~12 pF; add external load caps to X1 and X2 to match crystal CL (each cap = (CL - 12) × 2 pF)." } ], "provenance": {@@ -180,5 +180,8 @@ "docs/501milft-datasheet.pdf", "viewers/symbol.html", "viewers/footprint.html"- ]+ ],+ "visibility": {+ "public": true+ } }